[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Intel · Canada, Toronto # Power Delivery Design Engineer Canada, Toronto Design Listed on Intel’s official careers site. Posted October 21, 2026. Check that it is still open and apply there. [Apply on Intel’s careers site →](https://intel.wd1.myworkdayjobs.com/External/job/Canada-Toronto/Power-Delivery-Design-Engineer_JR0287983) [OpenNash Jobs](https://jobs.opennash.com/) / [Intel](https://jobs.opennash.com/companies/intel/) / Power Delivery Design Engineer ## Job description ### Job Details Job Description: Are you passionate about computing and AI accelerators? Do you thrive on innovation and want to disrupt the industry? Are you eager to work with leading AI hardware engineers on Intel's latest architecture? If you love collaborating with diverse teams to create best-in-class AI compute platforms, Intel's GPE department has exciting opportunities for you. As a member of the GPE team, you will develop hardware and platform solutions for Intel products, including the newest IPs targeted at next-generation GPUs and AI accelerators. You will have the opportunity to engage in enabling technologies in PCB design, manufacturing, testing, and debugging. We are a winning team with a clear vision of delivering competitive and cutting-edge products, and we are committed to building the best products and developing the best skills for our team. ### Key Responsibilities Work on end-to-end power delivery design and development, from initial concept to implementation of power delivery requirements and ecosystem enabling power integrated circuits. Own power integrity simulation for the platform power delivery network: build and correlate VRM-to-die PDN models, run DC IR-drop and AC target-impedance analysis, and perform transient droop and Ldi/dt studies across die, package, and PCB to set the decoupling and stack up strategy before layout is committed. Apply knowledge of power conversion topologies, including components, compensation circuits/stability analysis, drop/droop analysis, simulation tools, and techniques, as well as PCB layout and design tools, to characterize performance and validate correlation of simulation modeling and results. Design and validate platform power conversion and management solutions, including energy management, and perform simulation and optimization for package and PCB, including stack up, power/ground noise plane assignment, decoupling solutions, and/or power sequencing requirements. ### Design for debug architect observability into the board from the start, including per-rail voltage and current sense points, Kelvin-sense and probe landing points, telemetry and current-monitor access (SVID/PMBus/IMON), rail-level isolation and enable control, and voltage-margining, so power-on and post-silicon issues can be isolated on the first board instead of a respin. ### Design for flexibility build configurability into the power delivery solution so a single board can support multiple SKUs and derivatives, using stuffing options for phase count and decoupling, pin-compatible dual-source regulator footprints, rail split/merge and current headroom for higher-power SKUs, and programmable load line, compensation, and VID range. Create and execute test plans to validate and characterize power delivery solutions. Correlate bench and VR test tool measurements with simulation results to improve simulation model accuracy and close the loop on power integrity assumptions. Conduct failure analysis and root cause investigations for power delivery issues, implementing corrective actions to prevent recurrence. Collaborate with silicon and platform architects to generate solutions and analyses, delivering content into platform design guides as solution collaterals for end customers. Collaborate with cross-functional teams, including board design, SW/FW, and systems validation, to ensure seamless integration of power delivery solutions. ### Qualifications Minimum Qualifications, you must possess the below minimum qualifications to be initially considered for this position. Bachelor's or Master's degree in Electrical Engineering or a related field. 5+ years of experience in: Designing low voltage, high current, multi-phase DC-DC switching regulators (buck, boost, etc.) to meet stringent targets, optimizing the design for transient response and conversion efficiency. Working with signal/power integrity and power delivery network simulation tools such as Cadence Sigrity PowerDC/PowerSI, Ansys SIwave etc. to develop accurate models of circuit design Design and optimize accurate power delivery simulation models using SPICE and time-based simulation tools (LTSpice, SIMPLIS etc.) based on SOC design power requirements. Power delivery network modeling across die, package, and PCB, including stackup, plane assignment, decoupling network design, and S-parameter extraction and correlation. Experience using oscilloscopes and DAQ for hardware troubleshooting and debugging. Interacting with Signal Integrity, Layout, and Mechanical engineers, with working knowledge of SI/PI, PCB layout, and mechanical aspects of board designs. Preferred Qualifications, are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience designing for debug and testability on power delivery hardware, including sense and telemetry instrumentation, voltage margining, and rail isolation for post-silicon bring-up. Experience designing configurable power delivery solutions that support multiple SKUs and derivative products from a single board design. Identify new technologies/interfaces and develop board power delivery architecture. Experience in project management, including leading projects and manage timelines and resources effectively. Familiarity with emerging technologies such as GaN power devices, switched capacitor topology, etc. Experience delivering products for high-volume production and cost optimization. Knowledge of board and power management (HW/SW/FW) debugging. Willing to provide hardware technical support to ODM/OEM board vendors. Willingness to travel globally to meet internal teams and external customers. ### Job Type Experienced Hire Shift: Shift 1 (Canada) ### Primary Location Canada, Toronto Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Annual Salary Range for jobs which could be performed in Canada Salary range dependent on a number of factors including location and experience. Work Model for this Role This role will require an on-site presence. - Job posting details (such as work model, location or time type) are subject to change. ### Canada Accommodation Intel is committed to a culture of accessibility. Intel provides accommodations to applicants and employees with disabilities. Find information and request accommodation here. ### ADDITIONAL INFORMATION - Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. ## At a glance - Posted by the employer: Oct 21, 2026 - First seen by OpenNash: Oct 25, 2026 - Last checked: Nov 1, 2026 - Listed for: 11 days - Location: Canada, Toronto[Apply on Intel’s careers site →](https://intel.wd1.myworkdayjobs.com/External/job/Canada-Toronto/Power-Delivery-Design-Engineer_JR0287983) ## Hiring at Intel - Open jobs: 801 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All Intel jobs](https://jobs.opennash.com/companies/intel/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Intel ### [Compiler Engineer](https://jobs.opennash.com/companies/intel/jobs/1fab6dbdf57f37783f70/) Canada, Toronto ### [Compiler Engineer - Triton and DSLs](https://jobs.opennash.com/companies/intel/jobs/18168f3d7968abcfd9f6/) Canada, Toronto ### [Compiler Engineering Graduate Intern](https://jobs.opennash.com/companies/intel/jobs/c95e1fc895866df8bd83/) Canada, Toronto ### [Compiler Engineering Intern](https://jobs.opennash.com/companies/intel/jobs/73f5130d832e86353c9f/) Canada, Toronto ## Similar jobs at other companies ### [Design Engineer (Power Electronics)](https://jobs.opennash.com/companies/abb/jobs/a437af1bd42871946fe2/) ABB · Helsinki, Uusimaa, Finland ### [Senior Design Engineer (Power Electronics)](https://jobs.opennash.com/companies/abb/jobs/3c0b85ef5c2ac381db09/) ABB · Helsinki, Uusimaa, Finland ### [Power Design Engineer, up to Staff](https://jobs.opennash.com/companies/qualcomm/jobs/e911e6ea8b1a176fc85e/) Qualcomm · Taipei, Taipei City, Taiwan ### [Power Integrity Design Engineer – PDN / EMIR - Cork, Ireland](https://jobs.opennash.com/companies/qualcomm/jobs/c04b8f138e447d9f0fa2/) Qualcomm · Cork, Ireland ### [R10236464 Staff Electrical Engineer (Power Supply Design)](https://jobs.opennash.com/companies/northrop-grumman/jobs/3eba56576bf83b04eb10/) Northrop Grumman OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. [ OpenNash ](https://opennash.com/) AI-native services firm that builds custom software and 24/7 AI agents. OpenNash Jobs is an OpenNash Applied AI project. [Book time with OpenNash](https://calendly.com/opennash/new-meeting?hide_gdpr_banner=1) Jobs - [Search jobs](https://jobs.opennash.com/search/) - [Companies](https://jobs.opennash.com/explore/) - [Hiring report](https://jobs.opennash.com/reports/hiring/) - [AI assistants](https://jobs.opennash.com/connect/) - [How it works](https://jobs.opennash.com/methodology/) OpenNash - [opennash.com](https://opennash.com/) - [Services](https://opennash.com/ai-agent-consulting/) - [OpenNash CX](https://opennash.com/cx/) - [AI Tools](https://opennash.com/ai-tools/) - [Blog](https://opennash.com/blog/) - [About](https://opennash.com/about/) Contact - [hello@opennash.com](mailto:hello@opennash.com) - [LinkedIn](https://www.linkedin.com/company/opennash) - [Support](https://jobs.opennash.com/support/) - [Privacy](https://jobs.opennash.com/privacy/) - [Terms](https://jobs.opennash.com/terms/) © 2026 OpenNash, Inc. Company names and public job postings belong to their respective owners. Employers control source availability and application decisions.