[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Intel jobs](https://jobs.opennash.com/companies/intel/) · [Search jobs](/search/) Intel · India, Bangalore # Analog Circuit Design Engineer India, Bangalore Design Listed on Intel’s official careers site. Posted September 30, 2026. Check that it is still open and apply there. [Apply on Intel’s careers site →](https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineer_JR0287600) [OpenNash Jobs](https://jobs.opennash.com/) / [Intel](https://jobs.opennash.com/companies/intel/) / Analog Circuit Design Engineer ## Job description ### Job Details Job Description: ### Role Overview As an Integrated Voltage Regulator (IVR) Design Engineer, you will be responsible for the architecture, design, and implementation of high-performance power management solutions directly integrated onto advanced processors (CPUs, GPUs, or SoCs). You will work at the intersection of Analog/Mixed-Signal IC design and Power Electronics to improve energy efficiency and performance in next-generation computing systems. ### Key Responsibilities Circuit Architecture and Design: Develop and refine analog topologies such as Operational Amplifiers (Op-Amps), Bandgap References, Data Converters (ADC/DAC), and Phase-Locked Loops (PLLs). ### Design and Simulation Perform transistor-level design using industry-standard tools (like Cadence Virtuoso). Conduct extensive Monte Carlo simulations, corner analysis, and noise analysis to ensure high yield and reliability. ### Layout Oversight Collaborate closely with layout engineers to guide critical placement and routing, focusing on matching, shielding, and minimizing parasitic capacitance/resistance. ### Verification Use SPICE-based simulators to verify circuit functionality against rigorous performance specifications (speed, power, gain, etc.). ### Post-Silicon Characterization Bench-test silicon prototypes in the lab to validate performance against pre-silicon models and debug hardware anomalies Qualifications: ### Required Technical Skills Transistor Fundamentals: Expert knowledge of MOSFET/BJT device physics, small-signal modeling, and aging effects. ### EDA Tool Proficiency Mastery of Cadence (Spectre/Virtuoso), Mentor Graphics, or Synopsys tool suites. ### Signal Integrity Deep understanding of thermal noise, jitter, crosstalk, and power supply rejection ratio (PSRR). ### Mixed-Signal Flow Familiarity with Verilog-A or Verilog-AMS for behavioral modeling of analog blocks. ### Qualifications Education: BS, MS, or PhD in Electrical Engineering (EE) with a concentration in Analog IC Design. ### Experience 3 - 7 years of experience in analog design (FinFET or planar CMOS nodes). ### Analytical Mindset Strong mathematical background for analyzing feedback systems and stability. ### Job Type Experienced Hire Shift: Shift 1 (India) ### Primary Location India, Bangalore Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. - Job posting details (such as work model, location or time type) are subject to change. ### ADDITIONAL INFORMATION - Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. ## At a glance - Posted by the employer: Sep 30, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 18 days - Location: India, Bangalore[Apply on Intel’s careers site →](https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Analog-Circuit-Design-Engineer_JR0287600) ## More jobs at Intel ### [Analog Circuit Design Engineering Manager](https://jobs.opennash.com/companies/intel/jobs/0b086c10bf42e9b1b7d3/) India, Bangalore ### [Analog Design Engineer](https://jobs.opennash.com/companies/intel/jobs/f8af096f7a6fd31f2831/) India, Bangalore ### [Board Level Power Delivery Design Engineer](https://jobs.opennash.com/companies/intel/jobs/f2aa02b9791a0c3a5ee7/) India, Bangalore ## Similar jobs at other companies ### [Senior Quantum Engineer - Cryo-CMOS Analog Circuit Design](https://jobs.opennash.com/companies/microsoft/jobs/6b112ef80b58b548db0b/) Microsoft · Denmark, Copenhagen, Kongens Lyngby ### [Senior Staff Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering](https://jobs.opennash.com/companies/sandisk/jobs/9c9c9ee8de475c168163/) Sandisk ### [Senior Technologist Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering](https://jobs.opennash.com/companies/sandisk/jobs/04c89e21c7a143aa3d7b/) Sandisk ### [Memory Circuit Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/26b6bf9f8b20500a5700/) Qualcomm · Bangalore, India ### [Analog Circuit Design - IO Design Engineer](https://jobs.opennash.com/companies/samsung-electronics/jobs/fe8b6b8c4ba5ea825c38/) Samsung Electronics · SSIR, Goldstone, Bangalore, India [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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