[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Intel · Us, OR # EDA Tools Software Engineer US, Oregon, Hillsboro Full-time $95,640.00-181,940.00 Software Engineering Listed on Intel’s official careers site. Posted October 28, 2026. Check that it is still open and apply there. [Apply on Intel’s careers site →](https://intel.wd1.myworkdayjobs.com/External/job/US-Oregon-Hillsboro/EDA-Tools-Software-Engineer_JR0287371) [OpenNash Jobs](https://jobs.opennash.com/) / [Intel](https://jobs.opennash.com/companies/intel/) / EDA Tools Software Engineer ## Job description ### Job Details Job Description: As a member of the PTD Litho Frame Automation Team (FRAT) in LTD (Logic Technology Development), you will be responsible for process design rule definition, construction and validation of lead certification Tape-in Collaterals for Intel's next generation process technology and products. You will be responsible for the validation and creation of VLSI layout that will enable fundamental process development. Your responsibilities will include but will not be limited to: - Verify VLSI layout adherence to complex layout design rules, specifically ownership in Quality Assurance of FRAT designs across all Intel process nodes - Troubleshoot design and PDK(Process Design Kit) verification issues with complex physical design flows, both industry standard and Intel tools and flows Write/update software code for cell design and testcases, verification and package design content for distribution CAD design development and support of LTD Tape-in Collateral Library for ALL Intel - Process Technology nodes including CR experimental Path Finding projects Collaborating, directing, extracting, executing designs and constructs that will be used for process implementation, monitoring, improvement and development well ahead of any other team in LTD. This interaction will be with a very diverse team including Litho, Integration, Device, Test Chip, Tape Out, and OPC and RET (Reticle Enhancement Team) experts. These designs will be used during development, refined and then made available for HVM (High Volume Manufacturing) ### Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. ### Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 6+ months of hands-on experience in the domain and demonstrated skills gained through internships, academic projects, coursework, or hands-on training OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with no prior professional experience Hands-on experience includes: Coursework and background should include VLSI design or CAD, programming in Python or C++, Semiconductor Device Physics or basic electrical circuit theory, Silicon manufacturing flows Preferred Qualifications: Familiarity with semiconductor processing/engineering or computer science (from coursework or internship or work experience) VLSI Circuit mask design layout and/or verification (from coursework or internship or work experience) Basic solid-state physics, optics and IC (Integrated Circuit) process flow (from coursework or internship or work experience) Programming skills in a high-level programming language (from coursework or internship or work experience) - Familiarity with UNIX/Linux platforms (from coursework or internship or work experience) Experience with Cadence Virtuoso, Klayout, and tools such as Calibre DRV or Calibre - Knowledge of design rule checks (DRC), ICV, or IC Validator software tools Experience with custom design and verification tools, debugging, and flow development - Strong communication and collaboration skills for cross-functional teamwork Proactive mindset with a focus on continuous improvement and learning For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. ### Immigration Sponsorship Information Job Type Experienced Hire Shift: Shift 1 (United States of America) ### Primary Location US, Oregon, Hillsboro Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $95,640.00-181,940.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. - Job posting details (such as work model, location or time type) are subject to change. ### ADDITIONAL INFORMATION - Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. ## At a glance - Posted by the employer: Oct 28, 2026 - First seen by OpenNash: Nov 1, 2026 - Last checked: Nov 1, 2026 - Listed for: 4 days - Location: US, Oregon, Hillsboro - Employment type: Full-time - Pay: $95,640.00-181,940.00[Apply on Intel’s careers site →](https://intel.wd1.myworkdayjobs.com/External/job/US-Oregon-Hillsboro/EDA-Tools-Software-Engineer_JR0287371) ## Hiring at Intel - Open jobs: 801 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All Intel jobs](https://jobs.opennash.com/companies/intel/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Intel ### [AI Data Science / Software Engineering PhD Intern New 2027](https://jobs.opennash.com/companies/intel/jobs/7ac2963768d4fde7954c/) US, Oregon, Hillsboro ### [CAD/EDA Tools Software Engineer](https://jobs.opennash.com/companies/intel/jobs/371b2d04002da8dab1fa/) US, Oregon, Hillsboro ### [Cloud Software Development Engineer](https://jobs.opennash.com/companies/intel/jobs/91cbcd2658c578a20327/) US, Oregon, Hillsboro ## Similar jobs at other companies ### [EDA/CAD Software Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/1eeed27545bac6256521/) Qualcomm · San Diego, California, United States of America ### [Enterprise Software Development (EDA Tools) Intern](https://jobs.opennash.com/companies/keysight-technologies/jobs/3b81d08cbf8fcd54c7db/) Keysight Technologies · Santa Rosa, California ### [Engineer / Senior Engineer – AI Model Enablement & Software Tools](https://jobs.opennash.com/companies/qualcomm/jobs/f0b2594a33a7d4625544/) Qualcomm · San Diego, California, United States of America ### [Intern Software Engineer / Agent Engineer - EDA - Austin 2027](https://jobs.opennash.com/companies/ibm/jobs/c7ecda7fc1c04a3b7d9d/) IBM · Austin, TX ### [Senior Staff Engineer, Motor Drives & Power Tools](https://jobs.opennash.com/companies/infineon-technologies/jobs/6490fa2021e3888a2374/) Infineon Technologies · El Segundo, CA OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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