[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Intel jobs](https://jobs.opennash.com/companies/intel/) · [Search jobs](/search/) Intel · India, Bangalore # PERC Rule Deck Development Engineer India, Bangalore Operations Listed on Intel’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Intel’s careers site →](https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/PERC-Rule-Deck-Development-Engineer_JR0286602) [OpenNash Jobs](https://jobs.opennash.com/) / [Intel](https://jobs.opennash.com/companies/intel/) / PERC Rule Deck Development Engineer ## Job description ### Job Details Job Description: We are looking for a PERC Runset Development Engineer to develop and Validate PERC (Programmable Electrical Rule Checker) rule decks. The role involves working closely with PDK Team and foundry to implement PERC and ensure design compliance. ### Rule Development - Develop, validate, and maintain complex PERC rule decks to identify electrical reliability violations (e.g., ESD paths, current density, voltage stress, and floating gates). ### Multi-Tool Integration - Develop and optimize verification flows across multiple EDA environments, ensuring consistency in results between Calibre PERC( preferred), Cadence Pegasus, and Synopsys tools. ### Cross-Functional Collaboration - Work closely with Device Physicists, Process Integration Engineers, and Analog Designers to translate reliability requirements into programmable rules. ### Debug and Analysis - Provide expert-level support to design teams in debugging PERC violations, distinguishing between true reliability risks and tool-induced false positives. ### Automation - Develop scripts (Python, SKILL, Tcl, or Perl) to automate the execution, reporting, and tracking of reliability checks across different design versions. ### Documentation - Maintain detailed documentation of reliability check-sets and create guidelines for designers to implement correct-by-construction layouts. ### Qualifications Required Skills: - Experience with PERC rule development (preferably using Calibre PERC). - Knowledge of ESD, latch-up and reliability verification. - Familiarity with SVRF, TVF, Python or Tcl scripting. - Strong debugging and problem-solving skills. - Knowledge of Linux and scripting (Python/Shell/Tcl) is desirable. - Experience with advanced technology nodes is an advantage. - Team player and be able to work with global teams. ### Preferred Qualifications - Bachelor's degree with 10+ years of experience, OR - Master's degree with 8+ years of experience, OR - PhD degree with 2+ years of experience in Electrical Engineering, Computer Engineering, Electronics or related field; semiconductor industry experience. - Basic AI experience is an added skill. ### Job Type Experienced Hire Shift: Shift 1 (India) ### Primary Location India, Bangalore Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will require an on-site presence. - Job posting details (such as work model, location or time type) are subject to change. ### ADDITIONAL INFORMATION - Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: India, Bangalore[Apply on Intel’s careers site →](https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/PERC-Rule-Deck-Development-Engineer_JR0286602) ## More jobs at Intel ### [AI Platform and Agentic Engineer](https://jobs.opennash.com/companies/intel/jobs/88764b96a2c970816e7e/) India, Bangalore ### [CPU Senior Floor Plan Engineer](https://jobs.opennash.com/companies/intel/jobs/7e3ce83842f00510511b/) India, Bangalore ### [Engineering Manager](https://jobs.opennash.com/companies/intel/jobs/2745bbf35c00094e479d/) India, Bangalore ### [Formal Verification Engineer](https://jobs.opennash.com/companies/intel/jobs/2170ef39bdc96187ce7c/) India, Bangalore ## Similar jobs at other companies ### [Lead PERC Rule Deck Development Engineer](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/aac9034118b7e9275f2d/) NXP Semiconductors · Noida ### [Deck Cadet](https://jobs.opennash.com/companies/royal-caribbean-group/jobs/f9157fc1a364595e839c/) Royal Caribbean Group ### [Houseman Wet Deck - Part Time](https://jobs.opennash.com/companies/marriott-international/jobs/4e868b98d976a7c76caa/) Marriott International ### [Product Management, Director- Synopsys ICV PERC Established Nodes Product Strategies](https://jobs.opennash.com/companies/synopsys/jobs/0f5f96ba549f8b785529/) Synopsys · Cairo, Egypt OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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