[Skip to main content](#main-content)

[ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/)

IBM · Bangalore, IND

# Logic Design Engineer

Bangalore, IND Design 

Listed on IBM’s official careers site. Posted October 22, 2026. Check that it is still open and apply there.
[Apply on IBM’s careers site →](https://ibm.dejobs.org/jobs/D4DA04EA723E47359782BE41FCF56A76/)

[OpenNash Jobs](https://jobs.opennash.com/) / [IBM](https://jobs.opennash.com/companies/ibm/) / Logic Design Engineer

## Job description

### Introduction

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation.

With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

### Your role and responsibilities

Your primary responsibilities will include:
- Define and document microarchitecture for assigned functional blocks, including pipeline structure, data-path organisation, and control logic.
- Author clean, synthesisable RTL in VHDL or SystemVerilog, adhering to team coding guidelines and lint/CDC/RDC cleanliness targets.
- Collaborate with architects to evaluate design alternatives and communicate area, power, and frequency trade-offs.
- Drive design debug across simulation, emulation, and post-silicon environments; develop debug strategies and root-cause RTL or logic issues efficiently.

### Own timing closure for assigned blocks
- analyse critical paths, apply SDC constraints, guide ECO strategies, and work with physical design to meet frequency targets.
- Review and sign off on verification plans, ensuring functional coverage goals align with the microarchitectural intent.
- Participate in design reviews and contribute to cross-project lessons-learned to improve team-wide processes.
- Mentor junior engineers on RTL quality, debug methodology, and timing fundamentals. Required technical and professional expertise
- 5-10 years in digital ASIC or processor logic design, Microarchitecture definition and specification authoring.
- RTL coding in SystemVerilog and/or VHDL
- Static timing analysis (STA) and SDC constraint authoring
- Timing closure — path analysis, ECOs, hold/setup fixing

### Design debug
- simulation, waveform analysis, emulation
- Logic synthesis (Synopsys DC, Cadence Genus, or equivalent)
- Lint, CDC, and RDC analysis tools (SpyGlass or equivalent)
- Familiarity with formal verification flows
- Cross-functional collaboration with physical design and DFT Preferred technical and professional experience
- Experience in high-performance processor, memory subsystem, or high-speed interconnect design (e.g. PCIe, NVLink, OpenCAPI).
- Exposure to power analysis and low-power design techniques (clock gating, power domains, UPF/CPF).
- Post-silicon bring-up and debug experience including lab instrumentation and JTAG-based debug flows.
- Familiarity with emulation platforms (Palladium, Zebu) for pre-silicon debug at speed.
- Track record of driving an RTL block from specification to tapeout on a commercial product. IBM is committed to creating a diverse environment and is proud to be an equal-opportunity employer.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender, gender identity or expression, sexual orientation, national origin, caste, genetics, pregnancy, disability, neurodivergence, age, veteran status, or other characteristics. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

## At a glance
- Posted by the employer: Oct 22, 2026
- First seen by OpenNash: Oct 26, 2026
- Last checked: Nov 2, 2026
- Listed for: 11 days
- Location: Bangalore, IND[Apply on IBM’s careers site →](https://ibm.dejobs.org/jobs/D4DA04EA723E47359782BE41FCF56A76/)

## More jobs at IBM

### [Chip Design Integration Engineer](https://jobs.opennash.com/companies/ibm/jobs/2d8f98b3f367b531f1bb/)

Bangalore, IND

### [IO Design Architecture Expert](https://jobs.opennash.com/companies/ibm/jobs/76c2d502278fb2c966a6/)

Bangalore, IND

### [Lead Analog Circuit Design Engineer](https://jobs.opennash.com/companies/ibm/jobs/4248dd40d9dbd1295d2e/)

Bangalore, IND

### [Linux Test Engineer](https://jobs.opennash.com/companies/ibm/jobs/ddb00e0928ff4243e0be/)

Bangalore, IND

## Similar jobs at other companies

### [Software Engineer - C++ / Digital Logic Design](https://jobs.opennash.com/companies/siemens/jobs/afc168c9cc5c1ae44fbb/)

Siemens 

### [Senior Logic Design Engineer - Microsoft Azure](https://jobs.opennash.com/companies/microsoft/jobs/218c1b875656e03bca74/)

Microsoft · Israel, Haifa, Multiple Locations

### [Lead Logic Design Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/6dd333afd34ce9ded283/)

Astera Labs · Bengaluru

OpenNash lists jobs from employers’ own careers sites and does not handle applications.
Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

[ OpenNash ](https://opennash.com/)

AI-native services firm that builds custom software and 24/7 AI agents.

OpenNash Jobs is an OpenNash Applied AI project.
[Book time with OpenNash](https://calendly.com/opennash/new-meeting?hide_gdpr_banner=1)

Jobs
- [Search jobs](https://jobs.opennash.com/search/)
- [Companies](https://jobs.opennash.com/explore/)
- [Hiring report](https://jobs.opennash.com/reports/hiring/)
- [AI assistants](https://jobs.opennash.com/connect/)
- [How it works](https://jobs.opennash.com/methodology/)

OpenNash
- [opennash.com](https://opennash.com/)
- [Services](https://opennash.com/ai-agent-consulting/)
- [OpenNash CX](https://opennash.com/cx/)
- [AI Tools](https://opennash.com/ai-tools/)
- [Blog](https://opennash.com/blog/)
- [About](https://opennash.com/about/)

Contact
- [hello@opennash.com](mailto:hello@opennash.com)

- [LinkedIn](https://www.linkedin.com/company/opennash)

- [Support](https://jobs.opennash.com/support/)

- [Privacy](https://jobs.opennash.com/privacy/)

- [Terms](https://jobs.opennash.com/terms/)

© 2026 OpenNash, Inc. Company names and public job postings belong to their respective owners. Employers control source availability and application decisions.