[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) IBM · Bangalore, IND # Chip Design Integration Engineer Bangalore, IND Design Listed on IBM’s official careers site. Posted October 26, 2026. Check that it is still open and apply there. [Apply on IBM’s careers site →](https://ibm.dejobs.org/jobs/1BB5716E1DE0411D98D0016051CDA955/) [OpenNash Jobs](https://jobs.opennash.com/) / [IBM](https://jobs.opennash.com/companies/ibm/) / Chip Design Integration Engineer ## Job description ### Introduction At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress. ### Your role and responsibilities As a Hardware Developer for Cognitive Systems, you will design, develop, test, and deliver offerings for Power & Z using the latest technologies. In this role, you will define the physical design and lay out the chip footprint, ensuring that all design constraints are met. Your primary responsibilities will include: ### Design and Develop Offerings - Design, develop, test, and deliver offerings for Power & Z using the latest technologies, defining the physical design and laying out the chip footprint. ### Perform Chip Integration - Interconnect all circuits, arrays, random logic, and I/O on the chip to a given set of ground rules for the silicon technology selected. ### Verify Design Constraints - Perform a series of checks (software runs) to verify that all design constraints are met, utilizing toolsets such as Cadence or other proprietary tools. ### Manage Chip Footprint - Define the physical design and lay out the chip footprint, ensuring effective use of space and meeting design requirements. Required technical and professional expertise ### Chip Design Development - Experience with designing, developing, testing, and delivering offerings for Power & Z using the latest technologies, including defining physical designs and laying out chip footprints. ### Chip Integration Engineering - Experience in interconnecting circuits, arrays, random logic, and I/O on chips to meet ground rules for selected silicon technologies. ### Design Constraint Verification - Experience with performing software runs to verify design constraints, utilizing toolsets such as Cadence or other proprietary tools. ### Silicon Technology Application - Experience applying knowledge of silicon technologies to ensure effective chip design and integration. ### Physical Design Optimization - Experience with optimizing physical designs to meet space and performance requirements. Preferred technical and professional experience ### Familiarity with Proprietary Tools - Experience with Cadence or other proprietary tools for performing software runs to verify design constraints is beneficial. ### Knowledge of Silicon Technologies - Understanding of various silicon technologies and their application in chip design and integration is advantageous. ### Physical Design Principles - Familiarity with principles of physical design optimization to meet space and performance requirements is desirable. IBM is committed to creating a diverse environment and is proud to be an equal-opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender, gender identity or expression, sexual orientation, national origin, caste, genetics, pregnancy, disability, neurodivergence, age, veteran status, or other characteristics. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status. ## At a glance - Posted by the employer: Oct 26, 2026 - First seen by OpenNash: Nov 2, 2026 - Last checked: Nov 2, 2026 - Listed for: 7 days - Location: Bangalore, IND[Apply on IBM’s careers site →](https://ibm.dejobs.org/jobs/1BB5716E1DE0411D98D0016051CDA955/) ## More jobs at IBM ### [IO Design Architecture Expert](https://jobs.opennash.com/companies/ibm/jobs/76c2d502278fb2c966a6/) Bangalore, IND ### [Lead Analog Circuit Design Engineer](https://jobs.opennash.com/companies/ibm/jobs/4248dd40d9dbd1295d2e/) Bangalore, IND ### [Linux Test Engineer](https://jobs.opennash.com/companies/ibm/jobs/ddb00e0928ff4243e0be/) Bangalore, IND ### [Logic Design Engineer](https://jobs.opennash.com/companies/ibm/jobs/9bc5fd8dbe5acfacb5fa/) Bangalore, IND ## Similar jobs at other companies ### [Product Engineer – AI-Driven Analog Chip Design](https://jobs.opennash.com/companies/siemens/jobs/87ba9ac3137cbdb4349c/) Siemens ### [Chip Design Integration Lead, Nitro Chip Design Team](https://jobs.opennash.com/companies/amazon/jobs/1d4f7239408648aff71b/) Amazon · IL, Tel Aviv ### [Chip Design Engineer, Graviton Chip Design Team](https://jobs.opennash.com/companies/amazon/jobs/915a33a73d2df5032ad0/) Amazon · IL, Haifa ### [Heterogeneous Integration Physical Design Engineer, Staff](https://jobs.opennash.com/companies/qualcomm/jobs/0de8eac292fcc579bc95/) Qualcomm · Hsinchu City, Taiwan ### [Senior Engineer, Systems Design – Systems Integration & Test](https://jobs.opennash.com/companies/thermo-fisher-scientific/jobs/b3d3e249c73f91dbeb80/) Thermo Fisher Scientific · Singapore OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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