[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All IBM jobs](https://jobs.opennash.com/companies/ibm/) · [Search jobs](/search/) IBM · Bangalore, IND # Physical Design Engineer- Static Timing Analysis (STA) Bangalore, IND Design Listed on IBM’s official careers site. Posted October 15, 2026. Check that it is still open and apply there. [Apply on IBM’s careers site →](https://ibm.dejobs.org/jobs/E7E645B397B4433BBBB25A9B55A82327/) [OpenNash Jobs](https://jobs.opennash.com/) / [IBM](https://jobs.opennash.com/companies/ibm/) / Physical Design Engineer- Static Timing Analysis (STA) ## Job description ### Introduction At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress. ### Your role and responsibilities We are looking for a highly skilled Physical Design Engineer with deep expertise in static timing analysis using Cadence Tempus. The ideal candidate will own timing closure across multiple blocks and top-level designs, working closely with synthesis, PD, and signoff teams to achieve high-performance, low-power SoC designs. ### KEY RESPONSIBILITIES - Lead timing closure strategy for full-chip / hierarchical SoC designs using ILM/ETM-based flows - Own signoff correlation between Tempus and other tools (PrimeTime, Innovus, etc.) - Drive timing closure across all PVT corners and MMMC modes; debug and resolve timing violations - Define and enforce timing methodology guidelines across the team; mentor junior/mid-level engineers - Develop and validate SDC constraints; perform timing ECOs (buffering, resizing, logic restructuring) - Drive automation - develop reusable TCL/Python scripts for timing analysis, reporting, and waiver management Analyze SI, crosstalk, and noise issues; handle Tempus SI for crosstalk delta-delay and glitch analysis Interface with Cadence EDA vendor for tool issues and new feature adoption - Participate in architecture and floorplan reviews to identify timing risks early - Contribute to DFM and low-power (CPF/UPF) timing signoff; generate timing reports and signoff closure ### Required technical and professional expertise Cadence Tempus (hands-on) Strong STA fundamentals MMMC / OCV / AOCV / POCV SDC expertise Timing ECO methodology ILM / ETM / QRC models SPEF correlation & back-annotation Tempus SI (crosstalk / glitch) CTS timing implications Multi-Vt / voltage island timing Innovus-Tempus in-design timing Cadence Conformal ECO Unix / Linux & TCL / Python scripting Advanced nodes (12nm or below) Physical-aware Tempus experience ### Preferred technical and professional experience Preferred Professional and Technical Expertise Experience with Cadence Innovus or other PD tools Understanding of IR/EM and power analysis impacts on timing - Familiarity with low-power design techniques (UPF/CPF) Exposure to signoff methodologies and tapeout cycles - Knowledge of automation and timing flow optimization IBM is committed to creating a diverse environment and is proud to be an equal-opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender, gender identity or expression, sexual orientation, national origin, caste, genetics, pregnancy, disability, neurodivergence, age, veteran status, or other characteristics. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status. ## At a glance - Posted by the employer: Oct 15, 2026 - First seen by OpenNash: Oct 19, 2026 - Last checked: Oct 19, 2026 - Listed for: 4 days - Location: Bangalore, IND[Apply on IBM’s careers site →](https://ibm.dejobs.org/jobs/E7E645B397B4433BBBB25A9B55A82327/) ## More jobs at IBM ### [Linux Test Engineer](https://jobs.opennash.com/companies/ibm/jobs/ddb00e0928ff4243e0be/) Bangalore, IND ### [Logic Design Engineer](https://jobs.opennash.com/companies/ibm/jobs/373e2d76981a2d557cb3/) Bangalore, IND ### [Physical Design Engineer](https://jobs.opennash.com/companies/ibm/jobs/9fee327820370e203c0c/) Bangalore, IND ### [Senior Logic Design Engineer](https://jobs.opennash.com/companies/ibm/jobs/11186dad618235216796/) Bangalore, IND ## Similar jobs at other companies ### [STA Design Engineer - Static Timing Analysis - Cork, Ireland](https://jobs.opennash.com/companies/qualcomm/jobs/bd7ae4505f66f3e5dbe5/) Qualcomm · Cork, Ireland ### [CAD Engineer - Static Timing Analysis & Physical Design](https://jobs.opennash.com/companies/apple/jobs/dbad98842ad493eb9c6c/) Apple · Haifa, Israel ### [CPU Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/27bd54e804c3da2d6519/) Qualcomm · Bangalore, India ### [Physical Design Engineer II](https://jobs.opennash.com/companies/microsoft/jobs/2d7f9c2e826bc117df12/) Microsoft · India, Karnataka, Bangalore ### [Physical Design Engineer, SoC Static Timing Analysis](https://jobs.opennash.com/companies/alphabet/jobs/ac496d8fdfae24904aeb/) Alphabet · Tel Aviv, Israel +1 more OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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