[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All GlobalFoundries jobs](https://jobs.opennash.com/companies/globalfoundries/) · [Search jobs](/search/) GlobalFoundries · Hsinchu, Hsinchu City, TW # Senior Engineer, ASIC Digital Design (System IP Verification) Hsinchu, Hsinchu City, TW Full-time Senior individual contributor Design Listed on GlobalFoundries’s official careers site. Posted October 19, 2026. Check that it is still open and apply there. [Apply on GlobalFoundries’s careers site →](https://careers.gf.com/careers/job/563980770505912) [OpenNash Jobs](https://jobs.opennash.com/) / [GlobalFoundries](https://jobs.opennash.com/companies/globalfoundries/) / Senior Engineer, ASIC Digital Design (System IP Verification) ## Job description About GF GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, power-efficient and high-performance solutions for high-growth markets. With global manufacturing operations across the U.S., Europe and Asia, GF is a trusted and holistic technology partner for customers around the world. GF’s talented global team remains focused every day on security, longevity and sustainability. For more information, visit www.gf.com. Introduction Join the System IP Verification team in Hsinchu to verify configurable system-level IP and subsystems for next-generation RISC-V processor platforms, including coherent memory subsystems, interconnect, low-power and SoC infrastructure IP. You will work with experienced engineers and receive technical mentoring while developing practical skills in verification planning, SystemVerilog/UVM, simulation, regression, coverage, automation and debug. You will collaborate with global architecture, RTL design, modeling, formal verification, software and system validation teams. ### Responsibilities - Learn the architecture and intended behavior of System IP blocks and subsystems, contribute to specification reviews and verification planning, and take increasing ownership of identifying and verifying functional, stress and corner-case scenarios. - Develop and maintain verification content using SystemVerilog/UVM or related methodologies, including tests, sequences, monitors, scoreboards, reference models, assertions, checkers and functional coverage, with mentoring from experienced engineers. - Run simulation and regression environments; analyze logs, waveforms and coverage results; isolate issues across RTL, testbench, protocol, configuration, clock/reset and subsystem-interaction boundaries; document findings and collaborate on root-cause analysis. - Apply Python, C/C++ or shell scripting to improve test generation, verification automation, regression analysis, data analysis and debug productivity. - Collaborate with architecture, RTL design, formal verification, modeling, software, infrastructure and processor/subsystem verification teams to improve product quality and contribute to agreed quality and project milestone objectives. - Document verification intent, implementation, results and lessons learned, and actively participate in technical reviews, team knowledge sharing and continuous improvement. ### Required Qualifications - Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science or a closely related field. - Strong academic foundation in digital logic, digital IC design, computer architecture, VLSI, embedded systems or a related area. - Hands-on programming or hardware-description experience in at least one of the following: Verilog/SystemVerilog, C/C++ or Python - Basic understanding of RTL design, simulation and debugging concepts, with the ability to analyze technical problems systematically. - Ability to learn unfamiliar concepts and clearly communicate technical assumptions, findings and open questions in written and spoken English. - Ability to work constructively with engineers across functions and geographical locations. ### Preferred Qualifications - Thesis, research, internship or project experience involving computer or processor architecture, RISC-V, cache or memory systems, interconnect/NoC, SoC integration, FPGA or digital verification. - Exposure to SystemVerilog/UVM, constrained-random verification, assertions/SVA, functional or code coverage, formal verification, performance modeling or processor/subsystem-level validation. - Familiarity with Linux, Git and EDA simulation or debug tools such as VCS/Verdi, Xcelium/SimVision, Questa, Verilator or equivalent tools. - Experience applying Python, C/C++ or shell scripting to verification automation, test - Interest in developing deeper expertise in cache coherency, memory ordering, interconnect protocols, low-power verification, functional safety/security or verification automation. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. ### No Recruitment Fee Policy GlobalFoundries is committed to ethical and transparent hiring practices. Candidates will not be charged any fees at any stage of the recruitment process. Any request for payment related to a GlobalFoundries employment opportunity is unauthorized and should be reported immediately. All legitimate recruitment communications are conducted exclusively through official GlobalFoundries channels. To report concerns or suspected recruitment fraud, please contact our Ethics & Compliance Office at global[dot]compliance[at]globalfoundries[dot]com or visit our official website. The Ethics & Compliance mailbox is not a recruitment channel. CVs/resumes submitted to this mailbox will not be reviewed, processed, or considered for employment opportunities. Please apply through the official GlobalFoundries careers site only. ### Information about our benefits you can find here [https://gf.com/about-us/careers/opportunities-asia](https://gf.com/about-us/careers/opportunities-asia) ## At a glance - Posted by the employer: Oct 19, 2026 - First seen by OpenNash: Oct 20, 2026 - Last checked: Oct 20, 2026 - Listed for: 1 day - Location: Hsinchu, Hsinchu City, TW - Employment type: Full-time[Apply on GlobalFoundries’s careers site →](https://careers.gf.com/careers/job/563980770505912) ## More jobs at GlobalFoundries ### [AI CPU Design Engineer](https://jobs.opennash.com/companies/globalfoundries/jobs/5697861763bbd5b8543a/) Bangalore, Karnataka, India, Pune, Maharashtra, Hyderabad, Telangāna ### [ATE HW Design Technical Leader](https://jobs.opennash.com/companies/globalfoundries/jobs/b85e1f456ea5e6ca6934/) Richardson, Texas, United States of America ### [Circuit Design Intern, Master's or PhD (Summer 2027)](https://jobs.opennash.com/companies/globalfoundries/jobs/61d62609f4e623fd37cd/) Austin, Texas, United States of America ### [Cryo CMOS Analog Design Engineer](https://jobs.opennash.com/companies/globalfoundries/jobs/c2d31c9de639e656a963/) Austin, Texas, United States of America, Santa Clara, California ### [Cryo RFIC Design Engineer, Quantum](https://jobs.opennash.com/companies/globalfoundries/jobs/3494811eaaa9076fe3d2/) Austin, Texas, United States of America, Santa Clara, California ## Similar jobs at other companies ### [ASIC/FPGA Design Verification Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/b9ebab233b8dca4884ac/) Qualcomm · Ottawa, Ontario, Canada ### [ASIC/FPGA Design Verification Engineer, Senior](https://jobs.opennash.com/companies/qualcomm/jobs/f7cc8fb7b0460376d7d6/) Qualcomm · Ottawa, Ontario, Canada ### [Sr. Lead ASIC design Engineer - Digital Design](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/6c6b694c70bacc9a74f5/) NXP Semiconductors · Hyderabad ### [Staff ASIC Digital Engineer (SOC Verification, PCIe) with 8 to 12 years of experience](https://jobs.opennash.com/companies/sandisk/jobs/3d2b2a850dec23a8b655/) Sandisk ### [Staff / Senior Staff Engineer Digital Design (RTL Design)](https://jobs.opennash.com/companies/infineon-technologies/jobs/bcdb3b7a61b92eede1d2/) Infineon Technologies · Singapore OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)