[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All GlobalFoundries jobs](https://jobs.opennash.com/companies/globalfoundries/) · [Search jobs](/search/) GlobalFoundries # Principal Engineer SoC Design Verification BANGALORE, Karnataka, India, Pune, Maharashtra, Mahārāshtra Senior individual contributor Design Listed on GlobalFoundries’s official careers site. Posted September 9, 2026. Check that it is still open and apply there. [Apply on GlobalFoundries’s careers site →](https://careers.gf.com/careers/job/563980770585237) [OpenNash Jobs](https://jobs.opennash.com/) / [GlobalFoundries](https://jobs.opennash.com/companies/globalfoundries/) / Principal Engineer SoC Design Verification ## Job description Principal SoC Verification About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries make possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com. Deliver Verification Excellence Across Advanced Platform Products At MIPS by GF Custom Silicon Business, verification is a critical component of product success. We are committed to building robust, scalable and reusable verification environments that ensure first-pass silicon success. We are seeking a highly experienced Verification Lead to define and drive the verification strategy for advanced platform products. Introduction The Principal SoC Verification Lead provides technical leadership for verification of complex Smart Analog & Sensor SoCs. The role is responsible for verification strategy, methodology, planning, execution, and signoff across subsystem and full-chip environments. This individual will drive verification quality across processor, accelerator, memory, connectivity, and sensor subsystems while ensuring comprehensive coverage and first-silicon success. ### Key Responsibilities As a Verification Lead, you will own or participate in the following: - Development of chip-level and subsystem-level verification strategies - Definition of test plans, coverage plans and verification methodologies including UVM - Leadership of verification engineers across internal and external resources - Lead verification of interfaces, bus interconnects, DMA engines, memory architectures, security and safety functions, data processing pipelines, peripherals and application use cases - Coordinate subsystem and SoC-level verification activities. - Development of scalable verification infrastructure and automation - Collaboration with architects and designers throughout the development cycle - Cross-functional coordination with physical design, emulation and other related engineering teams - Ownership of verification closure and signoff readiness Verification Strategy - Define verification architecture for complex SoCs. - Develop verification plans aligned with architecture and product requirements. - Establish signoff criteria and coverage closure methodology. ### Environment Development - Lead development of UVM-based verification environments. - Define reusable verification components and infrastructure. - Drive scalable verification frameworks across multiple SoC programs. ### SoC Verification Leadership - Lead verification of: - CPU subsystems - Interconnects - DMA engines - Memory architectures - Security and safety functions - Sensor data processing pipelines - Coordinate subsystem and SoC-level verification activities. ### Coverage & Metrics - Drive closure of: - Functional coverage - Code coverage - Assertions - Safety requirements coverage - Define verification KPIs and dashboards. ### Technical Leadership - Mentor senior verification engineers. - Lead reviews and verification signoff decisions. - Drive adoption of advanced verification methodologies. ### Required Qualifications - Minimum BS and 15+ years of relevant industry experience - Extensive experience in UVM-based verification - Experience verifying complex SoCs - Experience building reusable verification environments - Experience defining and tracking coverage metrics ### Preferred Qualifications - Experience with emulation and prototyping - Experience with safety and security verification - Experience with performance verification - Experience leading globally distributed teams GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. ### Information about our benefits you can find here [https://gf.com/about-us/careers/opportunities-asia](https://gf.com/about-us/careers/opportunities-asia) ## At a glance - Posted by the employer: Sep 9, 2026 - First seen by OpenNash: Oct 13, 2026 - Last checked: Oct 20, 2026 - Listed for: 41 days - Location: BANGALORE, Karnataka, India, Pune, Maharashtra, Mahārāshtra[Apply on GlobalFoundries’s careers site →](https://careers.gf.com/careers/job/563980770585237) ## More jobs at GlobalFoundries ### [AI CPU Design Engineer](https://jobs.opennash.com/companies/globalfoundries/jobs/5697861763bbd5b8543a/) Bangalore, Karnataka, India, Pune, Maharashtra, Hyderabad, Telangāna ### [ATE HW Design Technical Leader](https://jobs.opennash.com/companies/globalfoundries/jobs/b85e1f456ea5e6ca6934/) Richardson, Texas, United States of America ### [Circuit Design Intern, Master's or PhD (Summer 2027)](https://jobs.opennash.com/companies/globalfoundries/jobs/61d62609f4e623fd37cd/) Austin, Texas, United States of America ### [Cryo CMOS Analog Design Engineer](https://jobs.opennash.com/companies/globalfoundries/jobs/c2d31c9de639e656a963/) Austin, Texas, United States of America, Santa Clara, California ### [Cryo RFIC Design Engineer, Quantum](https://jobs.opennash.com/companies/globalfoundries/jobs/3494811eaaa9076fe3d2/) Austin, Texas, United States of America, Santa Clara, California ## Similar jobs at other companies ### [SoC Design Implementation Engineer (Up to Principal Level)](https://jobs.opennash.com/companies/qualcomm/jobs/0d64d20c8f0296e2bb0e/) Qualcomm · Ho Chi Minh, Hồ Chí Minh, Vietnam ### [SoC Design Verification Engineer (Up to Principal Level)](https://jobs.opennash.com/companies/qualcomm/jobs/07fc1a63fb397059f4c8/) Qualcomm · Ho Chi Minh, Hồ Chí Minh, Vietnam ### [Principal SOC Performance Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/4978befbe1d83beb7e57/) Microsoft · India, Karnataka, Bangalore ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk ### [Senior Principal Engineer SoC Design](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/3d1ab7b6a27095a411b6/) NXP Semiconductors · Pune OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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