[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All General Dynamics jobs](https://jobs.opennash.com/companies/general-dynamics/) · [Search jobs](/search/) General Dynamics · Boise, ID # ASIC FPGA Engineer | General Dynamics Boise, ID, US Full-time Operations Listed on General Dynamics’s official careers site. Posted October 2, 2026. Check that it is still open and apply there. [Apply on General Dynamics’s careers site →](https://www.gd.com/careers/asic-fpga-engineer-boise-id-us-2026-75304-gdms-opportunity) [OpenNash Jobs](https://jobs.opennash.com/) / [General Dynamics](https://jobs.opennash.com/companies/general-dynamics/) / ASIC FPGA Engineer | General Dynamics ## Job description ### Responsibilities for this Position ASIC FPGA Engineer ID 2026-75304 US-ID-Boise US-UT-Salt Lake City US-Telework-Telework Required Clearance: Secret, obtainable within reasonable time based on requirements Posted Date: 10/2/2026 Category: Engineering-Hardware Employment Type: Full Time Hiring Company: General Dynamics Mission Systems, Inc. ### Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience. ### Clearance Requirements Department of Defense Secret security clearance obtainable within reasonable time based on requirements. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. Responsibilities for this Position Role and Position Objectives As an ASIC/FPGA Engineer for our Idaho Scientific group, you will be a member of a cross-functional team responsible for designing and deploying secure system solutions. You will contribute to FPGA design, simulation, verification, and documentation efforts that support secure, mission-critical products. ### Key Responsibilities Create test and simulation plans that establish functional criteria. Define module interfaces and contribute to device design and simulation activities. Contribute to system architecture, system simulation, and detailed design approaches for assigned work. Support the FPGA development flow, including high-level design, synthesis, place and route, timing, and power or resource utilization. Verify test results, analyze performance, and document designs and results. Develop technical engineering products using established standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle. Work independently and with a cross-functional team to complete assigned tasks. Knowledge, Skills, and Abilities Strong written and verbal communication skills, including the ability to clearly report information relevant to sound ASIC/FPGA design decisions. Working knowledge of ASIC/FPGA engineering processes, concepts, principles, and design tools. Ability to grasp and apply new information quickly, multi-task, and think creatively when solving technical problems. Keeps current with relevant ASIC/FPGA technology trends and identifies appropriate opportunities to apply AI for continuous improvement and innovation. Ability to communicate issues, impacts, and corrective actions with project leaders and internal work groups. ### Required Qualifications and Experience Ability to obtain and maintain a security clearance. Degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field. Ability to clearly capture complex technical concepts in writing for both technical and general audiences. Strong analytical and problem-solving skills. Proven FPGA RTL development experience with a strong body of work in VHDL or Verilog development. Fluent in VHDL or Verilog hardware description languages. Fluent in embedded C or C++ programming. Experience developing test bench simulations. Experience with Xilinx Vivado and/or Altera Quartus software. Strong understanding of computer architecture. ### Preferred Qualifications and Experience Active U.S. security clearance. Working knowledge of applied cryptography. Experience applying principles of cybersecurity to operational technology and embedded systems. Experience reverse engineering hardware and software. Knowledge of the secure boot process. Experience developing RISC-V or other CPU microarchitectures. Experience with PCI Express or DDR controllers. ### Our Commitment to You An exciting career path with opportunities for continuous learning and development. Research oriented work, alongside award winning teams developing practical solutions for our nations security Flexible schedules with every other Friday off work, if desired (9/80 schedule) Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more See more at gdmissionsystems.com/careers/why-work-for-us/benefits Location The preferred work location is Idaho Scientific headquarters in Boise, Idaho, or Salt Lake City, Utah. Salary Note This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled. Combined Salary Range USD $103,585.00 - USD $110,000.00 /Yr. Company Overview General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team! Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans PI287476827 ## At a glance - Posted by the employer: Oct 2, 2026 - First seen by OpenNash: Oct 19, 2026 - Last checked: Oct 19, 2026 - Listed for: 17 days - Location: Boise, ID, US - Employment type: Full-time[Apply on General Dynamics’s careers site →](https://www.gd.com/careers/asic-fpga-engineer-boise-id-us-2026-75304-gdms-opportunity) ## More jobs at General Dynamics ### [ASIC FPGA Engineer Entry Level | General Dynamics](https://jobs.opennash.com/companies/general-dynamics/jobs/7eb59e014312f8f88906/) Boise, ID, US ### [Electrical Engineer Intern | General Dynamics](https://jobs.opennash.com/companies/general-dynamics/jobs/8a7cdaaf0c329fb75b9d/) Boise, ID, US ### [Embedded Security Engineer | General Dynamics](https://jobs.opennash.com/companies/general-dynamics/jobs/75daffa365f3d4fe85af/) Boise, ID, US ### [Embedded Software Engineer Entry Level | General Dynamics](https://jobs.opennash.com/companies/general-dynamics/jobs/80e5251382c63087b1d6/) Boise, ID, US ### [Embedded Software Engineer Intern | General Dynamics](https://jobs.opennash.com/companies/general-dynamics/jobs/32514c89afa4fac47564/) Boise, ID, US ## Similar jobs at other companies ### [ASIC & FPGA Design Engineer - E2](https://jobs.opennash.com/companies/lockheed-martin/jobs/4510ab87f7a931bd10e6/) Lockheed Martin · Liverpool, NY ### [ASIC & FPGA Design Engineer Sr](https://jobs.opennash.com/companies/lockheed-martin/jobs/90d5256c62b52a8fdb0d/) Lockheed Martin · Boulder, CO ### [FPGA Firmware Engineer / FPGA Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/44db9bb8d5725623875a/) Qualcomm · San Diego, California, United States of America ### [Specialist, Electrical Engineering - FPGA/ ASIC Hardware Engineer](https://jobs.opennash.com/companies/l3harris-technologies/jobs/d7eee643510adf5fd184/) L3Harris Technologies · Cincinnati, OH ### [ASIC/FPGA Methodology Engineer (TERADYNE, North Reading, MA)](https://jobs.opennash.com/companies/teradyne/jobs/1e4483bea16319a530b1/) Teradyne · North Reading, MA, US [Jobs in Boise, ID](/locations/us/id/boise/)[Jobs in Idaho](/locations/us-id/)[Operations jobs](/functions/operations/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)