[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cisco Systems jobs](https://jobs.opennash.com/companies/cisco-systems/) · [Search jobs](/search/) Cisco Systems · Armenia # ASIC Physical Design Engineer Armenia Hybrid Full-time Design Listed on Cisco Systems’s official careers site. Posted October 16, 2026. Check that it is still open and apply there. [Apply on Cisco Systems’s careers site →](https://careers.cisco.com/global/en/job/CISCISGLOBAL2025096EXTERNALENGLOBAL/ASIC-Physical-Design-Engineer) [OpenNash Jobs](https://jobs.opennash.com/) / [Cisco Systems](https://jobs.opennash.com/companies/cisco-systems/) / ASIC Physical Design Engineer ## Job description This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact Lead macro-level RTL-to-GDSII physical implementation and signoff. Collaborate with Front-End teams to translate architecture into optimal physical design. Perform synthesis, floorplanning, placement, Clock Tree Synthesis, and routing. Optimize power, performance, and area while maintaining design correctness through formal verification. Execute static timing analysis, physical verification, formal checks, and signoff closure to ensure reliable, high-quality silicon. Analyze and resolve Electromigration and IR-drop issues to meet reliability and performance signoff targets. ### Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field. 5+ years of hands-on experience in ASIC design and physical implementation. Proven track record in ASIC physical design and verification preferably in complex SoC or block-level projects. Deep knowledge of block-level synthesis, place-and-route (PnR), and timing closure. Experience with industry-standard PnR and signoff tools (e.g., Synopsys, Cadence). ### Preferred Qualifications Broad understanding of physical design methodologies, integration, and implementation flows. Experience in physical verification (LVS, DRC) and signoff processes. Familiarity with physical design EDA toolchains and end-to-end workflows. Advanced expertise in STA, timing closure, and constraint management. Proficiency in scripting (Tcl, Python, or Perl) for automation and productivity improvements. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. ## At a glance - Posted by the employer: Oct 16, 2026 - First seen by OpenNash: Oct 18, 2026 - Last checked: Oct 18, 2026 - Listed for: 2 days - Location: Armenia - Work arrangement: Hybrid - Employment type: Full-time[Apply on Cisco Systems’s careers site →](https://careers.cisco.com/global/en/job/CISCISGLOBAL2025096EXTERNALENGLOBAL/ASIC-Physical-Design-Engineer) ## More jobs at Cisco Systems ### [ASIC Design Verification Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/14a5f06c435467bc4714/) Armenia ### [Standard Cells Characterization Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/db8efcc8216346491c53/) Armenia ### [AI Infrastructure Engineer - GoLang, Kubernetes, Dockers, Linux - 8-12 years](https://jobs.opennash.com/companies/cisco-systems/jobs/d7b4e9feb0a817fbd8ff/) Bangalore, India ### [AI-Driven ASIC Physical Design Principal Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/a260f7ee14f00181b086/) San Jose, California, United States of America ### [ASIC Design Engineer Technical Lead](https://jobs.opennash.com/companies/cisco-systems/jobs/748126c6708cca314cf7/) San Jose, California, United States of America ## Similar jobs at other companies ### [ASIC/FPGA Design Verification Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/b9ebab233b8dca4884ac/) Qualcomm · Ottawa, Ontario, Canada ### [ASIC/FPGA Design Verification Engineer, Senior](https://jobs.opennash.com/companies/qualcomm/jobs/f7cc8fb7b0460376d7d6/) Qualcomm · Ottawa, Ontario, Canada ### [Physical Design Engineer II](https://jobs.opennash.com/companies/microsoft/jobs/2d7f9c2e826bc117df12/) Microsoft · India, Karnataka, Bangalore ### [Silicon Physical Design CAD Engineer](https://jobs.opennash.com/companies/microsoft/jobs/d047141045a6e2b56e7a/) Microsoft · India, Karnataka, Bangalore ### [ASIC Physical Design Engineer (RDSS Intern)](https://jobs.opennash.com/companies/nvidia/jobs/550870e0a8712f1e58e6/) NVIDIA · Taiwan, Hsinchu OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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