[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cisco Systems jobs](https://jobs.opennash.com/companies/cisco-systems/) · [Search jobs](/search/) Cisco Systems · Caesarea, Israel # ASIC Physical Design Engineer Caesarea, Israel Full-time Design Listed on Cisco Systems’s official careers site. Posted June 22, 2026. Check that it is still open and apply there. [Apply on Cisco Systems’s careers site →](https://careers.cisco.com/global/en/job/CISCISGLOBAL2017139EXTERNALENGLOBAL/ASIC-Physical-Design-Engineer) [OpenNash Jobs](https://jobs.opennash.com/) / [Cisco Systems](https://jobs.opennash.com/companies/cisco-systems/) / ASIC Physical Design Engineer ## Job description Cisco Silicon One is seeking a Physical Design Engineer. Meet the Team The Physical Design team within Cisco Silicon One owns backend methodology and flow development from RTL to GDS. The team plays a critical role in developing high-quality VLSI designs for some of Cisco's most advanced silicon products. We work with the latest silicon technologies and processes to build large-scale, complex devices that push the boundaries of feasibility. You will collaborate with experienced engineers across architecture, design, verification, and implementation to deliver high-performance silicon. Your Impact You will be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. As a Physical Design Engineer, you will contribute to backend implementation work across key stages of chip design, helping move complex designs from RTL toward GDS. You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team. Contribute to physical synthesis, place and route, optimization, and timing closure for complex VLSI designs. Support design floor planning and implementation planning in collaboration with senior physical design engineers. Analyze timing, congestion, power, area, and design-rule issues and help drive them toward closure. Work with physical design verification flows, including LVS and DRC, to support clean implementation handoff. Partner with cross-functional teams to debug implementation issues and improve backend flow quality. ### Minimum Qualifications B.Sc. or M.Sc. in Electrical Engineering or a related field. 2+ years of hands-on experience in VLSI backend design or a relevant physical design domain. Strong understanding of the Place & Route flow. Hands-on experience with physical synthesis, place and route, optimization, timing closure, or design floor planning. ### Preferred Qualifications Understanding of physical construction and integration concepts across backend implementation. Knowledge of physical design verification methodology, including LVS and DRC. Familiarity with physical design EDA tools such as Synopsys, Cadence, or similar platforms. Ability to learn independently, take ownership of assigned tasks, and work effectively with teammates. Strong problem-solving skills and attention to detail in complex technical environments. #li-as6 Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. ## At a glance - Posted by the employer: Jun 22, 2026 - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 18, 2026 - Listed for: 118 days - Location: Caesarea, Israel - Employment type: Full-time[Apply on Cisco Systems’s careers site →](https://careers.cisco.com/global/en/job/CISCISGLOBAL2017139EXTERNALENGLOBAL/ASIC-Physical-Design-Engineer) ## More jobs at Cisco Systems ### [ASIC Physical Design CAD Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/0d88de2d6f0a1b3dee4b/) Caesarea, Israel ### [Hardware Engineer- HW Board Design](https://jobs.opennash.com/companies/cisco-systems/jobs/81027fa351f09fd4ca42/) Caesarea, Israel ### [IC Package Design Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/b7958b95f21465b87bfb/) Caesarea, Israel ### [Logic Design Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/085e2ea1e3565b83dce1/) Caesarea, Israel ### [Physical Design Manager](https://jobs.opennash.com/companies/cisco-systems/jobs/ef0de82879c29f5c83dd/) Caesarea, Israel ## Similar jobs at other companies ### [ASIC/FPGA Design Verification Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/b9ebab233b8dca4884ac/) Qualcomm · Ottawa, Ontario, Canada ### [ASIC/FPGA Design Verification Engineer, Senior](https://jobs.opennash.com/companies/qualcomm/jobs/f7cc8fb7b0460376d7d6/) Qualcomm · Ottawa, Ontario, Canada ### [Physical Design Engineer II](https://jobs.opennash.com/companies/microsoft/jobs/2d7f9c2e826bc117df12/) Microsoft · India, Karnataka, Bangalore ### [Silicon Physical Design CAD Engineer](https://jobs.opennash.com/companies/microsoft/jobs/d047141045a6e2b56e7a/) Microsoft · India, Karnataka, Bangalore ### [ASIC Physical Design Engineer (RDSS Intern)](https://jobs.opennash.com/companies/nvidia/jobs/550870e0a8712f1e58e6/) NVIDIA · Taiwan, Hsinchu OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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