[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cisco Systems jobs](https://jobs.opennash.com/companies/cisco-systems/) · [Search jobs](/search/) Cisco Systems · Caesarea, Israel # Senior Asic Design - Cisco Silicon One Caesarea, Israel Full-time Senior individual contributor Design Listed on Cisco Systems’s official careers site. Posted August 4, 2026. Check that it is still open and apply there. [Apply on Cisco Systems’s careers site →](https://careers.cisco.com/global/en/job/CISCISGLOBAL1447134EXTERNALENGLOBAL/Senior-Asic-Design-Cisco-Silicon-One) [OpenNash Jobs](https://jobs.opennash.com/) / [Cisco Systems](https://jobs.opennash.com/companies/cisco-systems/) / Senior Asic Design - Cisco Silicon One ## Job description Meet the Team Join the Cisco Silicon One Front-End Design team, at the core of Cisco’s silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation. We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of what’s possible. Cisco Silicon One™ is transforming the industry with a unified, programmable architecture powering Cisco’s future routing portfolio and shaping the Internet for decades to come. ### Your Impact - Write and review micro-architecture specifications Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements - Contribute to full chip integration, timing methodology, and analysis - Collaborate with verification engineers to resolve bugs and achieve coverage closure - Work with the physical design team to close timing and PnR issues - Support design methodology evolution and best practices - Perform debug, root-cause analysis, and post-silicon validation in the lab ### Minimum Qualifications B.Sc./M.Sc. in Electrical Engineering from a top university RTL design experience Familiarity with UVM and functional verification methodologies ### Preferred Qualifications Experience with MATLAB simulations and bit-exact modeling environments Familiarity with mixed-signal systems and environments Knowledge and hands-on experience with Clock Domain Crossing (CDC) Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. ## At a glance - Posted by the employer: Aug 4, 2026 - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 18, 2026 - Listed for: 100 days - Location: Caesarea, Israel - Employment type: Full-time[Apply on Cisco Systems’s careers site →](https://careers.cisco.com/global/en/job/CISCISGLOBAL1447134EXTERNALENGLOBAL/Senior-Asic-Design-Cisco-Silicon-One) ## More jobs at Cisco Systems ### [ASIC Physical Design CAD Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/0d88de2d6f0a1b3dee4b/) Caesarea, Israel ### [ASIC Physical Design Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/6ade4af539ac57131cc7/) Caesarea, Israel ### [Hardware Engineer- HW Board Design](https://jobs.opennash.com/companies/cisco-systems/jobs/81027fa351f09fd4ca42/) Caesarea, Israel ### [IC Package Design Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/b7958b95f21465b87bfb/) Caesarea, Israel ### [Logic Design Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/085e2ea1e3565b83dce1/) Caesarea, Israel ## Similar jobs at other companies ### [Silicon Physical Design CAD Engineer](https://jobs.opennash.com/companies/microsoft/jobs/d047141045a6e2b56e7a/) Microsoft · India, Karnataka, Bangalore ### [Senior Security Engineer (Cisco / Fortinet) Capelle aan den IJssel, Zuid-Holland Capelle aan den IJssel, Zuid-Holland ENGINEERING / DESIGN STUDIES / METHODS ENGINEERING / DESIGN STUDIES / METHODS Permanent](https://jobs.opennash.com/companies/vinci/jobs/801642e644c186e47ad4/) VINCI · Capelle aan den IJssel, Zuid-Holland ### [Staff Physical Design Engineer - Custom Silicon Group](https://jobs.opennash.com/companies/qualcomm/jobs/fabbe4056864b0076098/) Qualcomm · Bangalore, India ### [ASIC/FPGA Design Verification Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/b9ebab233b8dca4884ac/) Qualcomm · Ottawa, Ontario, Canada ### [Manager, Silicon Circuit Co-Design — Silicon Co-Design Group](https://jobs.opennash.com/companies/nvidia/jobs/d10b9778d20e032db54d/) NVIDIA · China, Shanghai OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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