[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cisco Systems jobs](https://jobs.opennash.com/companies/cisco-systems/) · [Search jobs](/search/) Cisco Systems · Armenia # Memory Layout Design Engineer Armenia Hybrid Full-time Design Listed on Cisco Systems’s official careers site. Posted October 5, 2026. Check that it is still open and apply there. [Apply on Cisco Systems’s careers site →](https://careers.cisco.com/global/en/job/CISCISGLOBAL2026849EXTERNALENGLOBAL/Memory-Layout-Design-Engineer) [OpenNash Jobs](https://jobs.opennash.com/) / [Cisco Systems](https://jobs.opennash.com/companies/cisco-systems/) / Memory Layout Design Engineer ## Job description This is a hybrid role with four days per week at Cisco’s Yerevan office. Meet the Team Our team is at the forefront of innovation, specializing in memory layout implementation for the Cisco Silicon One platform that powers the world’s most advanced switches and routers. We are a dynamic, international team dedicated to pushing the boundaries of high-performance networking technology. We offer a unique environment where technical excellence meets real-world impact. We value transparency, clear communication, and a collaborative spirit that bridges geographical divides to deliver ground breaking silicon solutions. Your Impact Implement high-quality memory layout implementation, specifically focusing on SRAM blocks to meet rigorous performance and reliability standards. Collaborate closely with international circuit design teams to translate schematics into robust physical designs that drive our core networking products. Perform post-layout simulations and implement necessary corrections to ensure DRC cleanliness and optimal integration with neighboring modules. Optimize layout designs for quality, visibility, and velocity to accelerate the delivery of critical silicon components. ### Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of total professional experience in physical design or layout. Proven experience working with industry-standard EDA tools such as Cadence or Synopsys. Experience with advanced node technologies such as TSMC 22nm, 12nm, 7nm, 5nm, or 2nm. ### Preferred Qualifications 3+ years of hands-on experience specifically in SRAM layout implementation. Experience working within a mixed-signal or custom design environment. Proficiency in performing EMIR/ERC closure and providing technical support for successful tapeouts. Background in circuit design, including reading schematics and running simulations. Proficiency in scripting languages (Tcl, Python, or Perl) for design automation. Strong ability to communicate effectively in English, both written and spoken, to support international collaboration. Demonstrated ability to work both independently and within a cross-functional, multi-site team environment. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. ## At a glance - Posted by the employer: Oct 5, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 13 days - Location: Armenia - Work arrangement: Hybrid - Employment type: Full-time[Apply on Cisco Systems’s careers site →](https://careers.cisco.com/global/en/job/CISCISGLOBAL2026849EXTERNALENGLOBAL/Memory-Layout-Design-Engineer) ## More jobs at Cisco Systems ### [ASIC Design Verification Technical Leader](https://jobs.opennash.com/companies/cisco-systems/jobs/a10a288e709a3b307326/) Armenia ### [Senior Physical Design Engineer - Signoff Methodology](https://jobs.opennash.com/companies/cisco-systems/jobs/90582d05a631b14af4ba/) Armenia ### [Senior RTL Design Engineer](https://jobs.opennash.com/companies/cisco-systems/jobs/200d2a649bd87cf3af33/) Armenia ### [ASIC DFT DV Technical Leader](https://jobs.opennash.com/companies/cisco-systems/jobs/f0a5f5fdaaa80dc3121e/) Armenia ## Similar jobs at other companies ### [Memory Circuit Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/26b6bf9f8b20500a5700/) Qualcomm · Bangalore, India ### [Senior Memory Systems Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/9e366288a971bf8f28bc/) Sandisk ### [System Design Engineer - Memory System](https://jobs.opennash.com/companies/sandisk/jobs/3c2f5f62d1ed5c94440e/) Sandisk ### [Staff Engineer Layout Design](https://jobs.opennash.com/companies/infineon-technologies/jobs/fdeab4792013c84fda64/) Infineon Technologies · Shanghai, 上海 ### [Design Verification Engineer — Memory Subsystem (Vancouver)](https://jobs.opennash.com/companies/qualcomm/jobs/41aeaaae7a0c3926967d/) Qualcomm · Vancouver, British Columbia, Canada OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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