[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Ciena jobs](https://jobs.opennash.com/companies/ciena/) · [Search jobs](/search/) Ciena · New Providence - NJ # Principal SI/PI Design Engineer New Providence - NJ Senior individual contributor $148,600 - $237,400 Design Listed on Ciena’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Ciena’s careers site →](https://ciena.wd5.myworkdayjobs.com/Careers/job/New-Providence---NJ/Principal-SI-PI-Design-Engineer_R029568) [OpenNash Jobs](https://jobs.opennash.com/) / [Ciena](https://jobs.opennash.com/companies/ciena/) / Principal SI/PI Design Engineer ## Job description As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. ### How You Will Contribute As an SI/PI Design Engineer, you will be an integral part of the Ciena engineering team and lead the electrical package design for custom in-house photonic, analog, and digital ICs supporting next generation optical modules. - Own and drive advanced package selection, new product BGA configuration and package structure Responsible for package/SIP layout, optimization, design verification and tapeout Interface and coordinate with cross-functional groups throughout Ciena on new product package selection, feasibility analysis and design - Work cross-functionally, understand trade-offs, constraints, and optimizing silicon floor plan, bump and package pin out Simulate and optimize signal/power integrity and RF performance of the package design Interface and work with CMs and vendors for the sourcing existing designs and future product development Must Haves: BS in Electrical Engineering or Physics - 5+ years hands on experience with IC package design Assets: Substrate design experience for RF, digital, high speed and mixed signal die Thorough understanding of signal and power integrity fundamentals - Proficient in Advanced Package Designer (APD)+SIP and/or Xpedition Package Designer (XPD) tools (Cadence highly preferred) Fluent in SI/PI and EM simulation tools such as SIWave, HFSS Experience in package design electrical review, SI/PI analysis Experience in package design for manufacturing reviews Familiar with package substrate technologies including 2.5-D IC and 3-D IC interposers Problem solver with strong engineering fundamentals Pay Range: The annual salary range for this position is $148,600 - $237,400 USD Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: New Providence - NJ - Pay: $148,600 - $237,400[Apply on Ciena’s careers site →](https://ciena.wd5.myworkdayjobs.com/Careers/job/New-Providence---NJ/Principal-SI-PI-Design-Engineer_R029568) ## More jobs at Ciena ### [Optoelectronic IC Package Design Director](https://jobs.opennash.com/companies/ciena/jobs/9f63f6027505c8f0ff35/) New Providence - NJ ### [Optical System Architect](https://jobs.opennash.com/companies/ciena/jobs/1de749b2720dd6cf95e1/) New Providence - NJ ### [Senior Fiber Coupling Engineer](https://jobs.opennash.com/companies/ciena/jobs/f54fa0a3e5470b3bf3dd/) New Providence - NJ ### [Senior Hardware Engineer](https://jobs.opennash.com/companies/ciena/jobs/ce5ec911837bf2a1ebae/) New Providence - NJ ### [Senior Optical Engineer](https://jobs.opennash.com/companies/ciena/jobs/7ab767d200bc37eaca99/) New Providence - NJ ## Similar jobs at other companies ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk ### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/) Sandisk ### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/) Microsoft · India, Karnataka, Bangalore ### [RISCV CPU Design Verification Principal Manager/ Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/312f1b332fbcaab058e8/) Qualcomm · Bangalore, India ### [Principal Engineer/Senior Staff Engineer- CPU Software & Hardware Co-Design Engineer (ML Systems)](https://jobs.opennash.com/companies/qualcomm/jobs/1fd1ae44127e47ec80dd/) Qualcomm · Bangalore, India OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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