[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Celestica jobs](https://jobs.opennash.com/companies/celestica/) · [Search jobs](/search/) Celestica · Shanghai, SH, CN # Sr. FPGA Engineer Shanghai, SH, CN Senior individual contributor Operations Listed on Celestica’s official careers site. Listed as of October 19, 2026. Check that it is still open and apply there. [Apply on Celestica’s careers site →](https://careers.celestica.com/job/Shanghai-Sr_-FPGA-Engineer-SH/1441452233/) [OpenNash Jobs](https://jobs.opennash.com/) / [Celestica](https://jobs.opennash.com/companies/celestica/) / Sr. FPGA Engineer ## Job description ### Req ID 140067 Region: Asia Country: China State/Province: Shanghai City: Shanghai Job Description: The FPGA/CPLD engineer will play a key role in designing, implementing, and validating FPGA/CPLD-based solutions for data center server, storage, and switching platforms. The role involves defining system FPGA/CPLD architecture, technical proposal and part selection, writing RTL code, running simulations, FPGA/CPLD schematic and PCB design review and validating designs on hardware. You will be responsible for optimizing designs to meet system requirements and working closely with hardware and software engineers to ensure full integration. This position works in a cross-functional team with designers, customers, and project leaders to ensure robust and high-quality product development. The FPGA/CPLD engineer will also help improve designs based on feedback from areas such as manufacturing, reliability, and testing. ### Job Responsibilities Work closely with system architecture, hardware designer and software designer to understand/define the architecture requirements Create the design specification, test plans, and reports to ensure design traceability. Cooperate with hardware engineer on the logic part schematic design /review etc. On-time delivery of the RTL design and module-level verification and test case definition Perform pre-synthesis and post-synthesis simulation and validation. Drive the entire back-end design flow including design constraints, floor-plan and timing analysis. Lead debugging and failure analysis efforts during FPGA/CPLD on-board validation. Collaborate with peers including different function team to ensure the successful delivery of high-performance systems As a mentor to junior engineers, provide training and technical guidance. Provide accurate and timely project schedule estimates, meet project milestone schedule Job Requirement: Bachelors or master's in computer science, Communication and System Engineering, Electrical Engineering or related fields BSEE with 10+ years of FPGA/CPLD experience or MSEE with 5+ years of experience, familiar with Xilinx and Intel(Altera)FPGA and Lattice CPLD/FPGA etc. In depth knowledge with Verilog, System Verilog, RTL design, FPGA/CPLD design, and FPGA/CPLD design tools (eg. ISE, Vivado, Quartuse-II, Diamond, Modelsim etc.) In depth knowledge with high speed serial protocols such as PCIe/USB/Ethernet/DDR/LVDS; Familiar with SPI, eSPI, I2C, UART, LPC, MDIO etc. low speed interface. Familiar with UVM constrained random coverage driven concepts, assertion based verification and functional coverage techniques. Proficient in understanding hardware schematics and PCB designs for FPGA/CPLD pinout constraints and on-board validation. Proficient in using oscilloscopes, multimeters, logic analyzers, and various hardware debugging and testing tools. - Excellent problem solving and hands-on debugging skills - Excellent communications skills and well English speaking/writing ability - Strong inter -personal skills and ability to understand customer needs, expectations and perspective - Demonstrated ability to multi-task on multiple projects Additional Prefer Requirement: In depth knowledge with data center server, storage, and switching platforms architecture, with expertise in FPGA/CPLD roles inside the system, FPGA/CPLD part selection, and technical proposal development. Familiar with hardware development processes with extensive experience in hardware design, bring-up, and troubleshooting, proficient in Intel/AMD X86 CPU architecture and power-up sequencing etc. In depth knowledge with secure boot design principles and implementation, providing suitable secure boot solutions for different systems. Proficient in C/C++, with experience in FPGA/CPLD feature software driver development and verification, familiar with MicroBlaze, Nios-II, or MCU development is a plus. Proficient in Shell/Python development, customizing scripts based on system requirements for testing purposes. Celestica is an equal opportunity employer. All qualified applicants will receive consideration for employment and will not be discriminated against on any protected status (including race, religion, national origin, gender, sexual orientation, age, marital status, veteran or disability status or other characteristics protected by law). At Celestica we are committed to fostering an inclusive, accessible environment, where all employees and customers feel valued, respected and supported. Special arrangements can be made for candidates who need it throughout the hiring process. Please indicate your needs and we will work with you to meet them. ### COMPANY OVERVIEW Celestica (NYSE, TSX: CLS) enables the world’s best brands. Through our recognized customer-centric approach, we partner with leading companies in Aerospace and Defense, Communications, Enterprise, HealthTech, Industrial, Capital Equipment and Energy to deliver solutions for their most complex challenges. As a leader in design, manufacturing, hardware platform and supply chain solutions, Celestica brings global expertise and insight at every stage of product development – from drawing board to full-scale production and after-market services for products from advanced medical devices, to highly engineered aviation systems, to next-generation hardware platform solutions for the Cloud. Headquartered in Toronto, with talented teams spanning 40+ locations in 13 countries across the Americas, Europe and Asia, we imagine, develop and deliver a better future with our customers. Celestica would like to thank all applicants, however, only qualified applicants will be contacted. Celestica does not accept unsolicited resumes from recruitment agencies or fee based recruitment services. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 12, 2026 - Last checked: Oct 19, 2026 - Listed for: 7 days - Location: Shanghai, SH, CN[Apply on Celestica’s careers site →](https://careers.celestica.com/job/Shanghai-Sr_-FPGA-Engineer-SH/1441452233/) ## More jobs at Celestica ### [DFT and Test Engineer](https://jobs.opennash.com/companies/celestica/jobs/989d1431ac3e59a37082/) Shanghai, SH, CN ### [Sr. Hardware Engineer](https://jobs.opennash.com/companies/celestica/jobs/1b0516c2728373650e26/) Shanghai, SH, CN ### [Sr. Power Engineer](https://jobs.opennash.com/companies/celestica/jobs/3da7f42446cd6b480bdc/) Shanghai, SH, CN ### [Sr. Thermal Engineer](https://jobs.opennash.com/companies/celestica/jobs/63ffa13b793ec0f67628/) Shanghai, SH, CN ### [Technical Project Lead](https://jobs.opennash.com/companies/celestica/jobs/31a4cdf490741f2915b6/) Shanghai, SH, CN ## Similar jobs at other companies ### [FPGA prototyping/FPGA design Engineer (Lead/Staff)](https://jobs.opennash.com/companies/qualcomm/jobs/5b9026c1d4f3d7d6d43a/) Qualcomm · Bangalore, India ### [Senior FPGA Engineer](https://jobs.opennash.com/companies/lockheed-martin/jobs/e2c813b6caddaf9d59e0/) Lockheed Martin · Gloucester, GBR ### [ASIC/FPGA Design Verification Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/b9ebab233b8dca4884ac/) Qualcomm · Ottawa, Ontario, Canada ### [Senior Firmware & FPGA Engineer](https://jobs.opennash.com/companies/eaton/jobs/a264ce7526c26ebd290d/) Eaton · Vantaa, FIN ### [Senior FPGA Engineer](https://jobs.opennash.com/companies/lam-research/jobs/dc0287fa50697c2edad1/) Lam Research · Fremont, CA, US OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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