[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Capgemini jobs](https://jobs.opennash.com/companies/capgemini/) · [Search jobs](/search/) Capgemini # Analog Layout Engineer (FinFET technology) Fundão, Lisboa - Expo, VNG - Cais Gaia Operations Listed on Capgemini’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Capgemini’s careers site →](https://www.capgemini.com/jobs/532693-en_GB+sap_btp) [OpenNash Jobs](https://jobs.opennash.com/) / [Capgemini](https://jobs.opennash.com/companies/capgemini/) / Analog Layout Engineer (FinFET technology) ## Job description CAPGEMINI ENGINEERINGAt Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.YOUR ROLEWe are seeking an experienced Analog Layout Engineer with strong expertise in FinFET technology. The candidate will design and implement analog layouts for advanced nodes, ensuring compliance with design rules and optimizing for performance, reliability, and manufacturability. ### Key responsabilities Develop analog layouts for circuits such as amplifiers, references, bias blocks and data converters in FinFET nodesApply best practices for DRC/LVS closure, including advanced tips and tricks for efficient debuggingPerform EM/IR analysis and implement layout changes to meet reliability targetsAddress parasitic effects through careful routing, shielding, and post-extraction correctionsImplement matching techniques (common-centroid, interdigitation, dummy devices) for precision circuitsCollaborate with circuit designers to optimize layout for performance and yield.Ensure compliance with color-aware routing and multi-patterning constraints (SADP/SAQP)YOUR PROFILEMinimum 5 years of hands-on experience in FinFET layout design for Analog IP developmentStrong knowledge of LDE effects (WPE, STI, LOD) and mitigation strategiesProficiency in industry-standard EDA tools (Cadence Virtuoso, Calibre, PVS)Familiarity with parasitic extraction flows and correlation techniquesUnderstanding of reliability mechanisms (BTI, HCI) and guard-banding in layoutExperience with advanced-node design rules and color-aware layoutKnowledge of EM/IR verification methodologies and sign-off flowsAbility to automate layout tasks using SKILL or Python scriptsWHAT YOU’LL LOVE ABOUT WORKING HEREJoin a multicultural and inclusive team environment.Enjoy a supportive atmosphere promoting work life balance.Hybrid work.Your career growth is central to our mission. Our array of career growth programs and diverse professionals are crafted to support you in exploring a world of opportunities.Access valuable training and certifications in cutting edge technologies.Engage in exciting national and international projects.Health and life insurance.Referral program with bonuses for talent recommendations.Great office locations.ABOUT CAPGEMINICapgemini is an AI-powered global business and technology transformation partner, delivering tangible business value. We imagine the future of organizations and make it real with AI, technology and people. With our strong heritage of nearly 60 years, we are a responsible and diverse group of 420,000 team members in more than 50 countries. We deliver end-to-end services and solutions with our deep industry expertise and strong partner ecosystem, leveraging our capabilities across strategy, technology, design, engineering and business operations. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: Fundão, Lisboa - Expo, VNG - Cais Gaia[Apply on Capgemini’s careers site →](https://www.capgemini.com/jobs/532693-en_GB+sap_btp) ## More jobs at Capgemini ### [RF Analog Layout Engineer (FinFET Technology)](https://jobs.opennash.com/companies/capgemini/jobs/0b07d761f78b4b4c563e/) Fundão, Lisboa - Expo, VNG - Cais Gaia ### [(Senior) Cloud Engineer (w/m/d)](https://jobs.opennash.com/companies/capgemini/jobs/d69f11d66c5629168835/) Muenchen, Stuttgart, Koeln, Hamburg, Frankfurt, Nuernberg, Erfurt, Dortmund, Berlin, Ratingen, Ingolstadt, Wolfsburg ### [(Senior) Cloud Engineer (w/m/d)](https://jobs.opennash.com/companies/capgemini/jobs/93494e171d0dd1908f79/) Muenchen, Stuttgart, Nuernberg, Frankfurt, Hamburg, Duesseldorf ### [(Senior) Cloud Transformation Manager](https://jobs.opennash.com/companies/capgemini/jobs/dbf05302e686f884c1f4/) Diegem ### [(Senior) DevSecOps Engineer (w/m/d)](https://jobs.opennash.com/companies/capgemini/jobs/c60997518ca00005576d/) Muenchen, Stuttgart, Frankfurt, Hamburg, Duesseldorf ## Similar jobs at other companies ### [Staff Engineer Analog Layout](https://jobs.opennash.com/companies/infineon-technologies/jobs/dae39b856c85418d4dfc/) Infineon Technologies · Hanoi ### [Staff Engineer Analog Layout](https://jobs.opennash.com/companies/infineon-technologies/jobs/a6206d71c9dd6693d96d/) Infineon Technologies · Penang ### [Senior Analog Mixed-Signal IC Layout Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/221d9e3fe5624daf8663/) Astera Labs · Singapore City ### [Senior Analog Layout Engineer](https://jobs.opennash.com/companies/ciena/jobs/1620135583ef2d96079e/) Ciena · Ottawa +1 more ### [Tech Lead Analog Mixed-Signal IC Layout Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/0e396d4d7516da1c993a/) Astera Labs · Singapore City OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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