[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Capgemini jobs](https://jobs.opennash.com/companies/capgemini/) · [Search jobs](/search/) Capgemini # Senior CAD Semiconductor Engineer Athinai, Thessaloniki/Steliou Kazantzidi Senior individual contributor Operations Listed on Capgemini’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Capgemini’s careers site →](https://www.capgemini.com/jobs/527569-en_GB+sap_btp) [OpenNash Jobs](https://jobs.opennash.com/) / [Capgemini](https://jobs.opennash.com/companies/capgemini/) / Senior CAD Semiconductor Engineer ## Job description Technical SkillsEDA / CAD Flow ExpertiseStrong experience with full EDA flowsSimulation, synthesis, place & route, verification, DFT flowsTools from Cadence, Synopsys, Siemens EDA (Mentor Graphics)Tool validation, qualification, and deploymentStrong experience withEDA licensing systems (FlexLM/Flexera)Tool versioning, release management, and regression validationGood understanding ofRTL design, verification flows, and physical design constraintsInteraction between tools and silicon quality/productivityKnowledge in ISO26262, DO-254 is a plus Infrastructure & AutomationStrong experience inLinux-based compute farms for EDA workloadsDistributed storage systems (NFS, parallel/distributed FS)CI/CD systems (Jenkins, GitLab CI or equivalent)Scripting and automationPython, Perl, Shell, TCLInfrastructure-as-code and automation mindsetExperience withMonitoring and performance optimizationBackup, disaster recovery, high availability AI / Modern Engineering ToolingPractical experience withAI/LLM-based tooling integration (e.g., Copilot, OpenAI, Gemini, Mistral)Hybrid AI infrastructure (cloud + on-prem GPU environments)Use cases such asWorkflow automationDebug assistanceKnowledge retrieval (RAG)Engineering productivity optimizationAdditional skillsObject-oriented programming conceptsFamiliarity withVersion control systems (Git, SVN, etc.)DevOps practices and toolchainsMissionDefine, deploy, and maintain EDA tool flows and CAD infrastructure supporting semiconductor design and verification activities across full SoC lifecycle.Drive the evaluation, benchmarking, and integration of EDA tools (Cadence, Synopsys, Siemens EDA, Arteris) and associated flows to maximize productivity, reliability, and scalability.Own the engineering infrastructure environment (compute, storage, licensing, CI/CD, automation) required for advanced chip design workloads.Collaborate with design, verification, and physical implementation teams to ensure efficient, robust, and scalable tool usage.Explore and integrate AI/ML-based tooling and workflows to improve engineering productivity (automation, debugging, optimization, knowledge extraction).Ensure optimal trade-offs between performance, cost, scalability, and usability of the CAD environment.Act as a key technical interface between internal engineering teams, management, and EDA vendors.Provide regular reporting on tool performance, usage, and roadmap alignment.Main ResponsibilitiesDefine, deploy, and maintain EDA flows for digital, mixed-signal, and verification activities (simulation, synthesis, P&R, DFT, signoff).Evaluate, benchmark, and qualify new EDA tools, releases, and methodologies before production deployment.Design and operate EDA infrastructure environments, includingCompute farms (Linux-based clusters for simulation and regression)Storage systems (NFS, distributed storage, backup/DR)License servers (FlexLM/Flexera)Develop and maintain automation frameworks forTool installation and configurationRegression and CI/CD pipelinesResource provisioning and monitoringImplement and manage CI/CD pipelines (e.g., Jenkins, GitLab CI) for design and verification workflows.Collaborate with engineering teams toOptimize tool usage and flowsDebug tool-related issuesImprove turnaround time and efficiencyMaintain strong interaction with EDA vendors (Cadence, Synopsys, Siemens)Tool support, issue resolution, roadmap alignmentLicensing strategy and capacity planningDefine and enforce best practices and standards for CAD usage and tool flows.Integrate AI-driven capabilities into engineering workflows, includingLLM-assisted scripting and automationAI-based log analysis, debug assistance, and workflow optimizationHybrid cloud/on-prem AI infrastructure for sensitive dataSupport security, compliance, and reliability requirements (e.g., ISO 27001 environments). ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Aug 1, 2026 - Last checked: Oct 18, 2026 - Listed for: 78 days - Location: Athinai, Thessaloniki/Steliou Kazantzidi[Apply on Capgemini’s careers site →](https://www.capgemini.com/jobs/527569-en_GB+sap_btp) ## More jobs at Capgemini ### [VLSI Safety Architect](https://jobs.opennash.com/companies/capgemini/jobs/599ad68dbda920bbda94/) Athinai, Thessaloniki/Steliou Kazantzidi ### [(Senior) Cloud Engineer (w/m/d)](https://jobs.opennash.com/companies/capgemini/jobs/d69f11d66c5629168835/) Muenchen, Stuttgart, Koeln, Hamburg, Frankfurt, Nuernberg, Erfurt, Dortmund, Berlin, Ratingen, Ingolstadt, Wolfsburg ### [(Senior) Cloud Engineer (w/m/d)](https://jobs.opennash.com/companies/capgemini/jobs/93494e171d0dd1908f79/) Muenchen, Stuttgart, Nuernberg, Frankfurt, Hamburg, Duesseldorf ### [(Senior) Cloud Transformation Manager](https://jobs.opennash.com/companies/capgemini/jobs/dbf05302e686f884c1f4/) Diegem ### [(Senior) DevSecOps Engineer (w/m/d)](https://jobs.opennash.com/companies/capgemini/jobs/c60997518ca00005576d/) Muenchen, Stuttgart, Frankfurt, Hamburg, Duesseldorf ## Similar jobs at other companies ### [Senior Product Development Engineer (Semiconductor Device Physics, Semiconductor Fabrication flow and design with 3 to 5 years)](https://jobs.opennash.com/companies/sandisk/jobs/50d6c12f032b4cdc1b62/) Sandisk ### [Semiconductor Process Modeling Engineer](https://jobs.opennash.com/companies/lam-research/jobs/b879de60cb7ce3604df0/) Lam Research · Tualatin, OR, US ### [半導體驗證工程師 Semiconductor Safety Engineer](https://jobs.opennash.com/companies/sgs/jobs/a64ddd7611ef75871d6d/) SGS · 興珍里, New Taipei City, Taiwan ### [Formal Verification CAD Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/31ec5eb21a89b05efb66/) Qualcomm · Bangalore, India ### [Verification CAD Engineer](https://jobs.opennash.com/companies/sandisk/jobs/51aba80a46f58dc40c79/) Sandisk [Operations jobs](/functions/operations/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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