[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design # Principal Design Engineer Senior individual contributor Design Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/Principal-Design-Engineer_R49256) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Principal Design Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. ### Job Title Principal Design Engineer (Memory) ### Location Cork Reports to: Design Engineering Director Job Overview: The Cadence Silicon Solutions Group (SSG) develop leading edge Intellectual Property (IP) for a variety of High-Tech Markets. The Cadence IP solutions allow our Customers to tackle IP-to-SoC development in a system context, enabling them to focus on product differentiation and to reduce time to volume. This is an opportunity to join a development team designing state-of-the-art DDR memory controllers to be used in a wide range of applications including Datacenter, Edge computing, Automotive, and AI. Cadence is a leading provider of IP solutions for the biggest names in the technology industry. The Principal Design Engineer will be based in Cork, as part of an experienced Controller IP Team with long established Controller development sites in Europe, US and India. ### Job Responsibilities Architect solutions for the latest DDR controller features and customer requirements. Design RTL in a highly configurable and automated environment. Work in small project teams. Work across disciplines with Design Verification, Support, Delivery, Application Engineers, PHY design team, etc. Utilize Cadence’s Design Automation flow and IP development tools. Develop high speed circuits and low power features. Improve quality and efficiency and help refine development process for greater productivity of the team through automation and improved methods. Participate in an engineering team to advance our product. ### Job Qualifications Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline. 10+ years’ experience in microelectronics/EDA industry. Experience of Verilog RTL Design essential. Experience of Metric Driven Verification (MDV) essential. Experience of Front-end design tools covering LINT, Synthesis, CDC Analysis essential. Experience of SoC Architecture and Development essential. Experience of Technical Team leadership essential. Excellent oral and written English essential. Self-motivated with excellent planning, interpersonal, and communication skills. ### Additional Skills/ Preferences Experience of AMBA protocols such as CHI, AXI, AHB & APB preferred. Experience of SystemVerilog for design preferred. Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred. ### Additional Information Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 18, 2026 - Listed for: 100 days[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/Principal-Design-Engineer_R49256) ## More jobs at Cadence Design ### [AI Intern - Technical Communications (System Design Analysis Group)](https://jobs.opennash.com/companies/cadence-design/jobs/3fd4e202987c9263bc42/) ### [Analog Design Engineer II](https://jobs.opennash.com/companies/cadence-design/jobs/32273bb1256173e417c3/) Nanjing ### [Analog/Mixed-Signal IC Design Co-Op/Intern (Summer 2026) / Stage/Co-Op en Conception de CI Analogiques/Signal Mixte (Été 2026)](https://jobs.opennash.com/companies/cadence-design/jobs/24328000d0824efdc101/) MOUNT-ROYAL ### [Application Engineer I: Physical Design - Synthesis and Digital Implementation](https://jobs.opennash.com/companies/cadence-design/jobs/4e2269ad4ab1e223170f/) Belo Horizonte ### [Application Engineer II: Analog IC Design and Simulation](https://jobs.opennash.com/companies/cadence-design/jobs/3973b64c3a637ee148b9/) Belo Horizonte ## Similar jobs at other companies ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk ### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/) Sandisk ### [Principal Controls Design Engineer](https://jobs.opennash.com/companies/siemens-energy/jobs/e8c7b76ed43903cf23f2/) Siemens Energy ### [Design Principal Engineering Development Mechanical Redwood City California United States Carrollton Texas New York](https://jobs.opennash.com/companies/equinix/jobs/394b8298248f6584ac53/) Equinix ### [Design Principal Engineering Development Mechanical Redwood City California United States Dallas Texas New York](https://jobs.opennash.com/companies/equinix/jobs/847704d1b367c8b281b9/) Equinix OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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