[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · GYEONGGI-DO # Principal Product Engineer – High-Speed IP SerDes GYEONGGI-DO Senior individual contributor Operations Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/GYEONGGI-DO-Seoul/Principal-Product-Engineer---High-Speed-IP-SerDes_R56168) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Principal Product Engineer – High-Speed IP SerDes ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. ### Position Overview Join a growing and dynamic IP team developing best-in-class digital and mixed-signal IP solutions. This role focuses on post-sales technical support for high-performance interface IP, working as part of a team supporting UCIe, PCIe, USB, DPHY, Ethernet, DDR, LPDDR, GDDR, and HBM PHYs. The Principal Product Engineer is a key technical leader and product owner, responsible for driving product engineering activities across the full lifecycle—from pre-sales engagement and pre-silicon integration to post-silicon bring-up and customer deployment. This role serves as a primary interface between customers and Cadence R&D, leading technical discussions, resolving complex issues, and ensuring successful product adoption. This position requires strong technical depth, customer-facing leadership, excellent communication skills, and the ability to drive execution across global, cross-functional teams. ### Key Responsibilitie - Act as the primary product engineering owner for SerDes subsystems (PCIE, USB, Ethernet, etc) at the customer leve - Lead customer engagements, drive technical discussions, design reviews, and deployment strateg - Own and drive resolution of complex subsystem integration and implementation issue Lead SoC integration reviews covering PHY and controller subsystem - Provide technical leadership for RTL, gate-level simulations, and timing closure strategie - Define and drive improvements to integration methodologies, checklists, and customer collatera - Lead post-silicon bring-up and debug activities, ensuring successful customer deploymen - Collaborate cross-functionally with R&D, validation, and applications teams to deliver product readines - Drive continuous improvement in customer experience, turnaround time, and engineering qualit - Mentor junior engineers and provide technical guidance across projects and team Leverage AI tools to improve debug efficiency, data analysis, and decision-making ### Position Requirements - Strong experience with high-speed interface IP Deep understanding of RTL design, gate-level verification, and simulation methodologies Experience with synthesis, STA, and timing closure; backend knowledge is a plus - Familiarity with DFT methodologies, test flows, and system validation approaches Skills & Qualifications [Required] Bachelor’s in electrical engineering, Computer Engineering, or related field with 7+ years of experience, or Master’s with 5+ years, or PhD with relevant experience - Proven ability to solve complex technical problems and drive root cause to closure Experience leading cross-functional technical efforts across design, validation, and customer teams - Strong communication skills with ability to influence customer and internal stakeholders Experience managing multiple priorities, escalations, and technical reviews - Demonstrated ability to represent the organization in customer-facing technical roles - Strong ownership mindset and ability to drive deliverables independently [Preferred] Experience with memory and/or high-speed communication interfaces (DDR, LPDDR, PCIe, Ethernet, UCIe, USB) Understanding of analog/mixed-signal design practices Experience in customer-facing silicon debug and bring-up environments - Familiarity with AI-assisted workflows and data-driven debug techniques We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: GYEONGGI-DO[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/GYEONGGI-DO-Seoul/Principal-Product-Engineer---High-Speed-IP-SerDes_R56168) ## More jobs at Cadence Design ### [Lead Product Engineer - Verification](https://jobs.opennash.com/companies/cadence-design/jobs/6cf7848d3a6c70fd1610/) GYEONGGI-DO ### [Principal Product Engineer - Innovus+](https://jobs.opennash.com/companies/cadence-design/jobs/9b6b66329a757735add5/) GYEONGGI-DO ### [Principal Product Engineer - Verification](https://jobs.opennash.com/companies/cadence-design/jobs/2beb86b30e7b0ca4ac85/) GYEONGGI-DO ## Similar jobs at other companies ### [regional senior product manager high jewelry](https://jobs.opennash.com/companies/richemont/jobs/b8c58b341994015c2f5f/) Richemont ### [regional marketing manager high jewelry product marketing](https://jobs.opennash.com/companies/richemont/jobs/13337c9b4b20963c4cd4/) Richemont ### [Principal Product Engineer (AI/ML & Advanced Data Analytics Lead), Heterogeneous Integration Group(HIG), High Bandwidth Memory (HBM) Product Engineering](https://jobs.opennash.com/companies/micron-technology/jobs/29cc05f041ccfbb4d2c7/) Micron Technology · Singapore ### [Principal Engineer, Product Development Engineering](https://jobs.opennash.com/companies/sandisk/jobs/6d7cd6c9e5d306dc30ff/) Sandisk ### [Senior/Principal Product Systems Engineer](https://jobs.opennash.com/companies/microsoft/jobs/c8554f8332bf5fab3098/) Microsoft · United Kingdom, Cambridgeshire, Cambridge OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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