[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · San Jose # Senior Principal Digital Design Engineer San Jose Senior individual contributor $154,000 to $286,000 Design Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Sr-Principal-Design-Engineer_R55165-1) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Senior Principal Digital Design Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. ### Position Overview As a Senior Principal Digital Design Engineer, you will be responsible for the design, development, and ongoing support of system-level memory IP models used in hardware-based verification products. You will work across a broad range of memory technologies and interfaces, including SDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS. In addition to developing new memory models, you will maintain and enhance existing products to ensure performance, quality, usability, and long-term customer support. This role is a highly collaborative individual-contributor position that requires strong RTL design and verification expertise, excellent debugging skills, and the ability to work directly with internal and external customers on complex emulation, simulation, and verification challenges. ### Key Responsibilities Design, develop, verify, and productize system-level memory IP models for hardware-based verification platforms. Develop memory models supporting technologies and interfaces such as LPDDR, HBM, NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS. Maintain, enhance, debug, and support existing memory IP products throughout their lifecycle. Develop high-quality RTL using Verilog/SystemVerilog, applying sound design and coding practices. Develop and execute verification strategies using industry-standard simulation and emulation tools and methodologies. Diagnose and resolve complex RTL, protocol, system, and customer issues through effective debugging and root-cause analysis. Create and maintain technical documentation for memory IP, including design specifications, user documentation, and product support materials. Work directly with internal and external customers to understand requirements, investigate issues, and develop effective solutions for emulation, simulation, and verification environments. Plan and manage individual project schedules, priorities, deliverables, and technical tasks while adapting to changing business and customer needs. Collaborate with cross-functional engineering teams to support cross-verification, knowledge sharing, and cross-training across memory IP products. Contribute to and help evolve engineering lifecycle processes, methodologies, and quality practices to ensure reliable, maintainable, and high-quality products. Proactively identify technical risks and opportunities for improvement and drive issues to resolution. ### Required Qualifications MSEE or equivalent advanced degree with a minimum of 5 years of significant experience designing complex protocols, RTL, and/or hardware systems. Extensive hands-on experience with Verilog/SystemVerilog RTL design. Strong understanding of RTL verification methodologies, tools, and flows. Demonstrated ability to debug complex hardware, RTL, protocol, and system-level issues. Strong analytical and problem-solving skills, with the ability to identify root causes and develop practical solutions. Excellent written and verbal communication skills in English. Proven ability to work effectively as an individual contributor while collaborating closely with engineering, product, and customer-facing teams. Strong organizational and planning skills, with the ability to manage multiple priorities, schedules, and deliverables in an agile and adaptive environment. High emotional intelligence and a collaborative approach to communication, problem-solving, and conflict resolution. ### Preferred Qualifications Experience with Cadence simulation and/or emulation products. Experience with hardware emulation, simulation, or other hardware-based verification platforms. Programming or scripting experience with Perl, Tcl/Tk, C-shell, or similar languages. Experience with memory subsystem architecture, design, and operation. Experience designing or verifying memory protocols such as LPDDR, HBM, NAND Flash, eMMC, SD, DFI, or UFS. Experience developing reusable IP models or verification components for complex SoC or system-level environments. What Success Looks Like Success in this role means delivering robust, reusable, and customer-ready memory IP models while continuously improving existing products. You will combine deep RTL and verification expertise with strong debugging, communication, planning, and collaboration skills to solve challenging problems and help advance the quality and capabilities of the overall memory IP portfolio. The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: San Jose - Pay: $154,000 to $286,000[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Sr-Principal-Design-Engineer_R55165-1) ## More jobs at Cadence Design ### [DSP Hardware Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/dac6d4c7af4a4d5a5b7d/) San Jose ### [Lead Analog IC Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/41a337490e8e814bb762/) San Jose ### [Lead Red Hat Linux Architect](https://jobs.opennash.com/companies/cadence-design/jobs/4304555936c674ce4b12/) San Jose ### [Mixed-Signal, Sr Principal Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/586c1eb9a71bb1464921/) San Jose ### [Principal AE, Serdes Design IP](https://jobs.opennash.com/companies/cadence-design/jobs/565e79527e05b7a29b5f/) San Jose ## Similar jobs at other companies ### [Staff / Senior Staff Engineer Digital Design (RTL Design)](https://jobs.opennash.com/companies/infineon-technologies/jobs/bcdb3b7a61b92eede1d2/) Infineon Technologies · Singapore ### [Senior / Staff Engineer - Digital Design](https://jobs.opennash.com/companies/infineon-technologies/jobs/6af7082b2823e36216a0/) Infineon Technologies · Singapore ### [Principal/ Sr Principal Digital Design Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/55bf35544b196196cda9/) Astera Labs · Taiwan ### [Digital Design Verification Engineer, Staff](https://jobs.opennash.com/companies/qualcomm/jobs/a645ad2a0d00db966bb8/) Qualcomm · Toronto, Ontario, Canada ### [Principal/ Sr.Principal Digital Design Engineer](https://jobs.opennash.com/companies/astera-labs/jobs/4c86e245b94b0b37992d/) Astera Labs · San Jose OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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