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Cadence Design · NOIDA

# Design Engineer II

NOIDA Design 

Listed on Cadence Design’s official careers site. Posted October 2, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/NOIDA/Design-Engineer-II_R56553)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Design Engineer II

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

### Role Overview

Key Responsibilities: Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.

### Advanced Verification

Champion the integration of formal verification, and AI-driven coverage analysis.

### Cross-Functional Collaboration

Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

### Required Qualifications

B.Tech/M.Tech in ECE with Experience in SystemVerilog/UVM and C/C++ for architectural modeling. Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe. Expertise in scripting (Perl, Python, or Tcl) for verification flow automation. Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations. We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Oct 2, 2026
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 16 days
- Location: NOIDA[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/NOIDA/Design-Engineer-II_R56553)

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Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

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