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Cadence Design · Multiple locations

# Sr Principal Design Engineer

Multiple locations Senior individual contributor Design 

Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/PUNE-04/Sr-Principal-Design-Engineer_R53296)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Sr Principal Design Engineer

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

### Experience

10- 15 years Location - Bangalore/Pune/ Responsibilities: · Complete DFT ownership of projects including: Test architecture definition. Identifying and implementing RTL changes for DFT. Performing scan insertion, LEC checks, low power CLP checks. Developing timing constraints for test mode timing closure. Scan and ATPG for different fault models. Boundary scan, ACJTAG, IEEE 1500 implementation and verification. IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.

Running zero delay and timing simulations and debugging on all the above aspects. Supporting post silicon bring up. Interacting with customers on DFT aspects and support Marketing & Pre-Sales team. Experience working on very high speed and low power designs. We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Jul 10, 2026
- Last checked: Oct 18, 2026
- Listed for: 100 days
- Location: Multiple locations[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/PUNE-04/Sr-Principal-Design-Engineer_R53296)

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Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

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