[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design # Principal Design Engineer Senior individual contributor Design Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/CORK-01/Principal-Design-Engineer_R51660) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Principal Design Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. ### Job Title Principal Design Engineer (Analog Mixed Signal / Memory) ### Location Cork Reports to: Design Engineering Director Job Overview: Lead Analog and Mixed Signal design of high speed memory interface analog components used in state-of-the-art DDR memory interface PHYs in leading edge technology nodes. Consisting of blocks such as IOs, amplifiers, comparators, drivers, duty cycle correctors, PLLs, DLLs, level shifters, etc. in advanced IC nodes in volume production. As Principal Design Engineer, you will provide technical direction and coordination to the analog IC design team and Identify opportunities to advance technology of analog design and participate in strategic internal analog IP development. ### Job Responsibilities - Design of High-Speed memory interface products at data rates up to and exceeding 36 Gbps on leading edge technology nodes (e.g. 5nm FinFET CMOS) - Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications - Work closely with Physical Design Engineers to design IC circuit blocks and PMA sections - Work with Technical Team Leads in the areas of circuit design and architects Mentor Junior Design Engineers when the project need arises - Work with global teams (US, India, China, EU), which work in different time-zones Job Qualifications: Successful candidate should be BEng, MEng qualified or have an equivalent qualification. - Minimum of 4 years of CMOS design experience, preferably in the area of CMOS SERDES, DDR or high-speed I/O IC design Should have a good understanding of jitter and signal equalization techniques - Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators - Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment Position requires proficiency in using CAD tools for circuit simulation, layout and physical verification Cadence tool experience and design experience in Lab test experience as part of silicon evaluation is advantageous Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 18, 2026 - Listed for: 100 days[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/CORK-01/Principal-Design-Engineer_R51660) ## More jobs at Cadence Design ### [AI Intern - Technical Communications (System Design Analysis Group)](https://jobs.opennash.com/companies/cadence-design/jobs/3fd4e202987c9263bc42/) ### [Design Engineering Architect](https://jobs.opennash.com/companies/cadence-design/jobs/c42d0049f16c381b7e3e/) ### [Lead Analog Layout Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/62d685886881e996bd7d/) ### [Lead Analog Layout Design Engineer (SerDes)](https://jobs.opennash.com/companies/cadence-design/jobs/5e3a1772b2ab6bb89176/) ## Similar jobs at other companies ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk ### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/) Sandisk ### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/) Microsoft · India, Karnataka, Bangalore ### [RISCV CPU Design Verification Principal Manager/ Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/312f1b332fbcaab058e8/) Qualcomm · Bangalore, India ### [Principal Engineer/Senior Staff Engineer- CPU Software & Hardware Co-Design Engineer (ML Systems)](https://jobs.opennash.com/companies/qualcomm/jobs/1fd1ae44127e47ec80dd/) Qualcomm · Bangalore, India OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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