[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · AUSTIN # Principal Design Engineer AUSTIN Senior individual contributor Design Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/AUSTIN/Principal-Design-Engineer_R54634) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Principal Design Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design Verification expert with good subsystem and SOC level verification. Must possess excellent debug skills. Expert in developing SV UVM based testbenches. Ability to coach and mentor less experience teammates. Should have worked on time-bounded projects leading to Si realization. Independently handle verification of complex modules or own significant piece in subsystem / SOC based verification. Define methodology for subsystem/SOC verification. Mentor less experienced engineers to bring them up as independent verification engineer. Follow systematic approach of metric driven verification with meticulous attention to quality and completeness. Should be able work closely across teams to meet delivery timelines. Required experience Worked on Subsystem / SOC level verification projects Experience in ARM based designs. In-depth knowledge SV-UVM Expertise in architecting, design and development of scalable verification environments from scratch. Define verification architecture and verification strategy Expertise in verification test plan development, test cases coding; Execute and debug test cases to achieve functional and code coverage goals Experience in C based testcase development Strong knowledge of AMBA protocols like AXI, ACE, APB, AHB. Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols Strong problem solving skills. Exhibit discipline, thoroughness and methodical approach in solving problems - Ability to work with stakeholders across cross-functional teams – Architecture, Design, Internal and External Customers Experience in mentoring junior engineers Self-driven and committed individual who can work in a fast paced project environment Desirable skills and experience Prior experience with Cadence tools and flows is highly desirable - Familiarity with ARM/CPU architectures is a plus Experience in developing c-based test cases for SOC verification Experience with assembly language programming Good knowledge of some of the protocols like UART, I2C, SPI, JTAG Embedded C code development and debug Formal Verification experience Cadence verification tool experience - Strong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. A strong positive attitude and ability to work in a team is a must. Self-motivated and willing take up additional responsibilities to contribute to team’s success. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 18, 2026 - Listed for: 100 days - Location: AUSTIN[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/AUSTIN/Principal-Design-Engineer_R54634) ## More jobs at Cadence Design ### [DFT Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/f2f8b52a9bff821f7f50/) AUSTIN ### [Design Engineer II](https://jobs.opennash.com/companies/cadence-design/jobs/22527f087f7464e5e115/) AUSTIN ### [Group Director, Design Engineering - Front End](https://jobs.opennash.com/companies/cadence-design/jobs/2745c57cc037325074f2/) AUSTIN ### [Lead Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/a0b4b9f419b350df76c0/) AUSTIN ## Similar jobs at other companies ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk ### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/) Sandisk ### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/) Microsoft · India, Karnataka, Bangalore ### [RISCV CPU Design Verification Principal Manager/ Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/312f1b332fbcaab058e8/) Qualcomm · Bangalore, India ### [Principal Engineer/Senior Staff Engineer- CPU Software & Hardware Co-Design Engineer (ML Systems)](https://jobs.opennash.com/companies/qualcomm/jobs/1fd1ae44127e47ec80dd/) Qualcomm · Bangalore, India OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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