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Cadence Design · Shanghai

# Lead Software Engineer - Logic Synthesis

Shanghai Manager or lead Software Engineering 

Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Lead-Software-Engineer---Logic-Synthesis_R56189)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Lead Software Engineer - Logic Synthesis

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

### Position Description

Responsible for development and maintenance of the synthesizer for Palladium. Implementation for new VHDL/Verilog feature support in synthesizer. Logic optimization and performance improvement in synthesizer.

### Position Requirement

This position requires a Bachelor or Master's degree in EE/CS/CE with 3-5 years of industry experience. Candidate should be proficient with C/C++, Operating system concepts. Design modeling using Verilog/SV, VHDL or SysC. Knowledge and experience in RTL modeling of BFMs along with exposure to verification methodologies using UVM and SC/TLM is preferable. EDA/CAD tool development experience or logic design verification experience is highly preferred.

Knowledge and experience in AI tools like Copilot or Claude code is preferred. Requires good communication skills, attention to details, and ability to work in multi-site/multi-person project. We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 7 days
- Location: Shanghai[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Lead-Software-Engineer---Logic-Synthesis_R56189)

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