[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · San Jose # RTL2GDS IC Sr. Principal Design Engineer San Jose Senior individual contributor $161,000 to $299,000 Design Listed on Cadence Design’s official careers site. Posted September 24, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/RTL2GDS-IC-Sr-Principal-Design-Engineer_R55850) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / RTL2GDS IC Sr. Principal Design Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. ### Job Description The ideal candidate will be energetic, innovative and enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology. Will drive Pre-sales and Post–sales activities at advanced nodes for Cadence Digital IC products. ### Key Responsibilities - Provide technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff - Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules - Conduct technical presentations and product demonstrations - Drive technical evaluations/benchmarks to success - Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements - Drive adoption and proliferation of Cadence tools and technologies Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements - Provide technical support, when developing business case for process improvement projects. Provide mentorship to junior engineers ### Job Requirements Requires a BS or MS or PhD in EE with/or 10-12 years industry related experience in design and EDA (Digital Implementation/Signoff) - Understands ASIC Design implementation process and steps - Strong hands-on experience with Place & Route (Innovus, ICC2, Fusion Compiler) Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler) Experience with EDA tools in the IC digital implementation & signoff flows (STA tools) Strong STA and SDC debugging abilities are required. Low power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus. Automation skills using Perl, Tcl and shell scripting essential Strong analytical & analysis skills covering digital implementation is critical. Proven track record and experience working in a fast paced environment Excellent customer interaction & presentation skills The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Sep 24, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 24 days - Location: San Jose - Pay: $161,000 to $299,000[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/RTL2GDS-IC-Sr-Principal-Design-Engineer_R55850) ## More jobs at Cadence Design ### [DSP Hardware Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/dac6d4c7af4a4d5a5b7d/) San Jose ### [Lead Analog IC Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/41a337490e8e814bb762/) San Jose ### [Lead Red Hat Linux Architect](https://jobs.opennash.com/companies/cadence-design/jobs/4304555936c674ce4b12/) San Jose ### [Mixed-Signal, Sr Principal Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/586c1eb9a71bb1464921/) San Jose ### [Principal AE, Serdes Design IP](https://jobs.opennash.com/companies/cadence-design/jobs/565e79527e05b7a29b5f/) San Jose ## Similar jobs at other companies ### [Manufacturing Engineer - Industrialization - GDS M/F](https://jobs.opennash.com/companies/safran/jobs/821fec44b2e9808c7a28/) Safran ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk ### [Principal Mechanical Design Engineer](https://jobs.opennash.com/companies/bouygues/jobs/fcb3d746f54a76b38df1/) Bouygues · MOTHERWELL, United Kingdom ### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/) Sandisk ### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/) Microsoft · India, Karnataka, Bangalore OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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