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Cadence Design · Shanghai

# Lead Design Engineer(Virtual Solution)

Shanghai Manager or lead Design 

Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Lead-Design-Engineer-Virtual-Solution-_R54953)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Lead Design Engineer(Virtual Solution)

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

### Key Responsibilities
- Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
- Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
- Develop end-to-end verification flows including: AVIP integration Testbench and system modeling Bare-metal / driver-level validation
- Optimize solutions for performance, scalability, and emulation efficiency
- Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows)
- Work closely with cross-functional teams (PE, AE, customers) to debug and resolve system-level issues
- Support customer enablement, including bring-up, debug, and solution deployment

### Required Qualifications

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with at least 3 years’ experience Strong expertise in high-speed protocols such as: PCIe, CXL, AMBA, UCIe, Ethernet (at least one) RTL design experience (SystemVerilog / Verilog) C/C++ development experience for modeling, testbench, or system integration Hands-on experience with Palladium / Protium / FPGA / emulation platforms is strongly preferred Good debugging skills for complex system integration issues

### Preferred Qualifications

Experience developing or using AVIP (Accelerated VIP) solutions Experience with end-to-end system validation flows (simulation → emulation → prototyping)
- Knowledge of UVM and verification frameworks
- Knowledge of Qemu/Gem5 or other system emulation projects Experience with multi-language environments (SV + C/C++ + Python)
- Familiarity with Emulation/Prototyping flows Exposure to AI/ML techniques applied to verification or tooling
- Strong problem-solving skills and ability to work independently Soft Skills Excellent English communication skills (both verbal and written) are required.

Strong learning capability and adaptability to new technologies Ability to collaborate across global teams Proactive mindset in problem solving and customer engagement We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Jul 10, 2026
- Last checked: Oct 18, 2026
- Listed for: 100 days
- Location: Shanghai[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Lead-Design-Engineer-Virtual-Solution-_R54953)

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Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

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