[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · Nanjing # Lead Design Engineer - Verification Nanjing Manager or lead Design Listed on Cadence Design’s official careers site. Posted September 30, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/Nanjing/Lead-Design-Engineer---Verification_R56556) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Lead Design Engineer - Verification ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. ### Primary Responsibilities - Contributor and senior technical engineer in the IP verification team, especially on high-performance Consumer PHYs including eUSB2v2, USB4-PHY, PCIe, eDP/DP, SATA, etc. ### Develop and maintain UVM-based verification environments - testbench architecture, agents/UVCs, sequences, scoreboards, register models (UVM RAL) and checkers, from block level to PHY top and controller+PHY subsystem level. - Create verification plans (vPlan) from protocol specifications and design documents; define functional coverage models, assertions (SVA) and testing strategy including corner conditions and error injection; drive coverage closure and signoff quality metrics. - Run and maintain regressions with simulation/regression platforms (Xcelium, vManager); triage failures, debug RTL/testbench issues with waveform tools (Verisium/SimVision), and track them to root cause and closure. - Apply low-power verification (power islands, state retention, isolation), clock/reset domain crossing checks (CDC/RDC), X-propagation, gate-level simulation and formal techniques as required by the project. - Integrate and configure commercial VIPs for serial protocols; verify firmware/hardware interaction and PHY bring-up/configuration flows together with firmware and design teams. - Work with the design team on testability of features, support lab bring-up and pre/post-silicon debug for global customers. - Partner closely with the Project Management Team to collaborate with various skill groups in Nanjing and multiple worldwide geographies to complete the IP deliverables with high quality; contribute to verification infrastructure, methodology and QA for customer releases. ### Position Requirements - MS / BS in Electrical/Computer Engineering or related degree. - 3+ years of relative industry working experience in digital/ASIC verification. - Solid hands-on experience with SystemVerilog and UVM; good knowledge of best practices and flows in constrained-random verification, functional coverage and assertion-based verification within an end-to-end methodology. - Knowledge of one or more industry serial standards, such as USB, DP, PCIe, Ethernet, etc., and their link training / power management / protocol layering. - Experience with verification planning and coverage-driven signoff. - Understanding basics of Analog Mixed-Signal verification, and a system view of physical interface IPs and their typical applications. - One Team mentality with a passion to innovate and a can-do attitude. - Strong cross-functional communication skills in both English and Mandarin. - Self-starter and highly motivated. Qualifications as Plus - Direct verification experience of high-speed serial interface link IPs (PHY/PCS/controller) in advanced technology nodes. ### Experience with Cadence verification tool suite - Xcelium, vManager, Verisium, JasperGold (formal/CDC), Palladium emulation. - Experience with low-power verification (UPF/CPF), gate-level simulation, and mixed-signal co-simulation. ### Scripting and automation skills - Python, Perl, Tcl, Makefile/regression infrastructure; interest in AI-assisted verification - Experience controller+PHY subsystem-level verification. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Sep 30, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 18 days - Location: Nanjing[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/Nanjing/Lead-Design-Engineer---Verification_R56556) ## More jobs at Cadence Design ### [Analog Design Engineer II](https://jobs.opennash.com/companies/cadence-design/jobs/32273bb1256173e417c3/) Nanjing ### [Design Engineer II](https://jobs.opennash.com/companies/cadence-design/jobs/c075fc71d6055466ac1b/) Nanjing ### [Layout Designer](https://jobs.opennash.com/companies/cadence-design/jobs/90e08a62b839e39065d7/) Nanjing ### [Lead Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/3df59837b65c4359b213/) Nanjing ## Similar jobs at other companies ### [Design Verification Engineer](https://jobs.opennash.com/companies/siemens/jobs/3469736e66b7ab53255d/) Siemens ### [NOC Design Verification Engineers (Engineer/Sr Engineer)](https://jobs.opennash.com/companies/qualcomm/jobs/012c5b47fdde2230c018/) Qualcomm · Bangalore, India ### [Design Verification Engineer II](https://jobs.opennash.com/companies/microsoft/jobs/e0e64d6ed7ea9cff1d03/) Microsoft · India, Karnataka, Bangalore ### [BT - Design Verification Sr Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/8a4545cadb1eb8810d4d/) Qualcomm · Bangalore, India ### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/) Microsoft · India, Karnataka, Bangalore OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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