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Cadence Design · Bangalore

# Design Engineer II

Bangalore Design 

Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Engineer-II_R55764)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Design Engineer II

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

### Job Opportunity

Foundry PDK Design Enablement Engineer Experience Level: 2–4 Years Department: Methodology & Flow Enablement Group Education: Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Technology, or a related field

### Position Overview

We are seeking a highly motivated Foundry Process Technology, PDK & DTCO Engineer with 2–4 years of experience to join our process technology group. In this role, you will bridge the gap between process technology and design, driving next-generation semiconductor technology through cutting-edge path-finding methodologies. The ideal candidate possesses a strong foundation in PDK enablement, physical verification decks, process/design interaction electrical studies, Spice model understanding and design automation.

### Key Responsibilities

PDK Enablement: Validate, deploy, and maintain foundational PDK components specifically tailored for advanced technology nodes.

### Technology Study Activities

Conduct rigorous standard cell, SRAM, and custom circuit benchmarking alongside interconnect optimization to maximize power, performance, and area (PPA).

### Automation & Methodology

Design, develop, and maintain robust scripts and automated execution flows for PDK enablement/validation and PDK analysis.

### Collaborative Path-Finding

Partner closely with internal DTCO groups to turn advanced device architectures into reality.

### Required Qualifications & Technical Skills Industry Experience

2–4 years of hands-on experience in semiconductor technology analysis, foundry PDK enablement, and the co-optimization of PDK components like LVS, DRC, Parasitic Extraction, spice models. Strong understanding of PDK design enablement flows. Exposure to multiple foundry & nodes is a plus.

### Device Physics

Strong fundamental understanding of CMOS device physics, including advanced architectures like GAA (Gate-All-Around), FinFETs, and planar MOSFETs.

### Physical Verification & EDA

Deep knowledge of Layout Versus Schematic (LVS), Design Rule Checking (DRC), Parasitic Extractions, and Spice models at transistor level. Cadence based tool knowledge is a plus.

### Tooling Familiarity

Direct experience or high proficiency with Cadence-based tool suites is highly advantageous.

### Team Collaboration

Proven experience interfacing with core PDK development teams, technology enablement units, or advanced technology benchmarking groups. We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 7 days
- Location: Bangalore[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Engineer-II_R55764)

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