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Cadence Design

# Lead Application Engineer

Manager or lead Operations 

Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/ZHUBEI-01/Lead-Application-Engineer_R55771)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Lead Application Engineer

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

### Responsibilities
- Engage with customers to understand verification challenges and identify suitable AI-assisted verification use cases. - UVM testbench and component generation
- Test and sequence generation - VIP integration and configuration
- Assertion and functional coverage generation
- Simulation failure triage and root-cause analysis
- Log and waveform analysis
- Verification flow automation
- Develop and optimize SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC designs.
- Develop reusable prompts, skills, agents, scripts, and AI-assisted workflows for customer applications.
- Conduct technical evaluations, benchmarks, demonstrations, workshops, and customer training.
- Troubleshoot UVM, simulation, AI integration, and verification flow issues.
- Collaborate with R&D, Product Engineering, and support teams to address customer requirements and technical issues.
- Develop technical collateral, AI use cases, reference flows, and best practices.

### Qualifications
- MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Five or more years of experience in digital design, functional verification, or EDA application engineering.
- Strong hands-on experience with SystemVerilog and UVM.
- Experience developing UVM environments, including agents, sequences, scoreboards, reference models, functional coverage, and register models.
- Strong understanding of constrained-random and coverage-driven verification methodologies.
- Experience integrating and debugging Verification IP in UVM-based environments.
- Experience with simulation, debug, coverage analysis, or low-power verification.
- Experience with Cadence tools such as Xcelium, Verisium, or VIP is a strong advantage.
- Strong scripting skills in Python, TCL, shell scripting, or Perl.
- Ability to translate verification challenges into practical and measurable AI-assisted solutions.
- Strong problem-solving, communication, presentation, and customer engagement skills.

### Preferred Qualifications
- Experience architecting reusable UVM environments for complex SoC or subsystem verification.
- Experience applying AI or automation to testbench generation, sequence generation, coverage, debug, or regression analysis.
- Familiarity with LLM APIs, prompt engineering, RAG, vector databases, agent-based workflows, MCP, or tool-calling frameworks.
- Experience deploying AI solutions in cloud-based or on-premises environments.
- Knowledge of CPU, interconnect, memory subsystem, low-power, or UPF verification.
- Familiarity with one or more protocols, including: - AMBA CHI, AXI, or AHB - USB or USB4 - LPDDR or HBM - UFS, UniPro, or M-PHY - PCI Express
- DisplayPort or eMMC We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 7 days[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/ZHUBEI-01/Lead-Application-Engineer_R55771)

## More jobs at Cadence Design

### [Lead Product Validation Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/e7c92e3ccec06885d483/)

### [Principal Product Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/98ce9a23cfb4d6548c04/)

### [Principal Project Manager - AE](https://jobs.opennash.com/companies/cadence-design/jobs/c0d96be638f4bb1723b3/)

### [Lead Software Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/1dbf0f81dc7be6e2a8e0/)

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Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

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