[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design # Principal Design Engineer Senior individual contributor Design Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/CORK-01/Principal-Design-Engineer_R54896) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Principal Design Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. ### Job Title Principal Analog Design Engineer (SERDES) ### Location Cork Reports to: Design Engineering Group Director Job Overview: The Principal Analog Design Engineer will take a Technical Leadership role on the PMA design team as part of a SERDES Product Team located at Cork, Ireland. ### Job Responsibilities - Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 5nm FinFET CMOS) - Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications - Work closely with Physical Design Engineers to design IC circuit blocks and PMA sections - Participate in technical leadership of the team in the areas of circuit design and SERDES architectures - Work with global teams (US, west coast and east coast), which work in different time-zones Job Qualifications: Candidate’s background should include a minimum of 7 years of experience in CMOS SERDES or high-speed I/O IC design and development BEng, MEng or PhD Qualified Working knowledge of a set of common SERDES standards and their electrical requirements - Must have a thorough understanding of jitter and signal equalization techniques - Proficient design experience in many of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators - Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment Additional Skills/Preferences: Cadence tool experience and design experience at >10Gbps and in Lab test experience as part of silicon evaluation is advantageous Interest in publishing academic papers and presenting at conferences e.g. ### ISSCC, JSSC Additional Information Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. ### Travel >5% We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/CORK-01/Principal-Design-Engineer_R54896) ## More jobs at Cadence Design ### [AI Intern - Technical Communications (System Design Analysis Group)](https://jobs.opennash.com/companies/cadence-design/jobs/3fd4e202987c9263bc42/) ### [Design Engineering Architect](https://jobs.opennash.com/companies/cadence-design/jobs/c42d0049f16c381b7e3e/) ### [Lead Analog Layout Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/62d685886881e996bd7d/) ### [Lead Analog Layout Design Engineer (SerDes)](https://jobs.opennash.com/companies/cadence-design/jobs/5e3a1772b2ab6bb89176/) ## Similar jobs at other companies ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk ### [Principal Mechanical Design Engineer](https://jobs.opennash.com/companies/bouygues/jobs/fcb3d746f54a76b38df1/) Bouygues · MOTHERWELL, United Kingdom ### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/) Sandisk ### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/) Microsoft · India, Karnataka, Bangalore ### [RISCV CPU Design Verification Principal Manager/ Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/312f1b332fbcaab058e8/) Qualcomm · Bangalore, India OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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