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Cadence Design · San Jose

# Sr Principal Engineer -SIPI

San Jose Senior individual contributor $178,500 to $331,500 Operations 

Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Sr-Principal-SI-PI-Engineer_R54206)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Sr Principal Engineer -SIPI

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Sr. Principal SI/PI Engineer This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position.

### Main Job Tasks and Responsibilities
- Work on test chip package design SI/PI optimization and verification.
- Work on evaluation board design optimization for best SI/PI performance.
- Provide extracted and measured channel models for chip designers in the R&D team.
- Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries.
- Review customer package and board designs and simulation results. Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC.
- Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
- Help with SI/PI related debug of test chips or customer ASICs in the lab.

### Position Requirements
- M.S. or Ph.D. Electrical Engineering (or similar degree)
- 3+ years of experience preferably working with high speed

### SerDes and PHYs
- Good understanding of high speed SerDes architecture
- Hands on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc.
- Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave
- Experience with IBIS-AMI model simulations
- Experience with simulation result to lab measurement correlation
- Good understanding of PCB and FCBGA design rules and requirements
- Strong debugging and problem-solving skills
- Excellent communication and presentation skills to effectively communicate with both customers and internal stake holders The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.

Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.

Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Jul 10, 2026
- Last checked: Oct 18, 2026
- Listed for: 100 days
- Location: San Jose
- Pay: $178,500 to $331,500[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Sr-Principal-SI-PI-Engineer_R54206)

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