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Cadence Design

# Lead Design Engineer

Manager or lead Design 

Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/PUNE-04/Lead-Design-Engineer_R54254-1)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Lead Design Engineer

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

### Role Overview

The DV Architect is a senior technical leadership role responsible for the strategic vision and infrastructure of verification for next-generation Tensilica advanced CPU cores and configurable processors. You will define the methodologies that ensure the functional integrity of highly complex instruction set architectures (ISA).

### Key Responsibilities

Methodology Strategy: Define and own the long-term DV architecture, focusing on scalability across multiple processor variants and generations.

### Verification Infrastructure

Architect simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments.

### Advanced Verification

Champion the integration of formal verification, and AI-driven coverage analysis.

### Cross-Functional Collaboration

Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements.

### Mentorship

Provide technical direction and set the standard for quality and metric-driven verification (MDV) across global teams.

### Required Qualifications

B.Tech/M.Tech in ECE with 4 to 8 years of experience in SoC/CPU/DSP verification. Deep expertise in SystemVerilog/UVM and C/C++ for architectural modeling. Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe. Expertise in scripting (Perl, Python, or Tcl) for verification flow automation. Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations.

We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Jul 10, 2026
- Last checked: Oct 18, 2026
- Listed for: 100 days[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/PUNE-04/Lead-Design-Engineer_R54254-1)

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