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Cadence Design · San Jose

# Principal Analog IC Design Engineer, High Speed SerDes

San Jose Senior individual contributor $136,500 to $253,500 Design 

Listed on Cadence Design’s official careers site. Posted October 1, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Principal-Analog-IC-Design-Engineer--High-Speed-SerDes_R55853-1)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Principal Analog IC Design Engineer, High Speed SerDes

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications. Candidate’s background should include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development.

Working knowledge of a set of common SerDes standards and their electrical requirements is a plus.
- Must have a thorough understanding of jitter and signal equalization techniques
- Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators
- Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification Cadence tool experience, lab test experience, and design experience at >10Gbps and in MS or PhD in EE The annual salary range for California is $136,500 to $253,500.

You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Oct 1, 2026
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 17 days
- Location: San Jose
- Pay: $136,500 to $253,500[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Principal-Analog-IC-Design-Engineer--High-Speed-SerDes_R55853-1)

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