[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · San Jose # Sr Principal HW Design Engineer-Emulation Acceleration System Platform San Jose Senior individual contributor $178,500 to $331,500 Design Listed on Cadence Design’s official careers site. Posted October 8, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Sr-Principal-HW-Design-Engineer-HW-Architect_R55582) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Sr Principal HW Design Engineer-Emulation Acceleration System Platform ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is the leader in hardware emulation-acceleration technologies and products. Looking for a hands-on Senior Principal HW Design Engineer who wants to expand their scope and grow their career. This position is located in our San Jose headquarter office, reports to the Sr Engineering Group Director of R&D and works in a growing talented organization. Our emulation-acceleration system platform is the most advanced industry-leading configurable scalable system, generation after generation, used in labs and datacenters. This position requires the engineer to architect systems, design boards, schematic entry, work with layout engineers to do PCB layout, signal integrity knowledge, bring-up, and sustain the current hardware platforms. Key responsibilities Responsible for architecture, design, bring-up, and sustain of hardware system platform. Continuously develop and apply technical domain expertise in Hardware Engineering. Maintain a strong, high level of competence in Electrical and/or Computer engineering to promote the incorporation of relevant technology into products and/or processes; and provide leadership and guidance to junior technical staff members. Establish and maintain Engineering Hardware standards, procedures, performance levels and documentation requirements. Propose and lead process improvement initiatives to drive breakthrough productivity and quality. Lead design reviews. Strong technical domain expertise in Electrical Engineering principles, concepts, and methods, and global standards compliance in order to work through technical issues of design integrity, manufacturability, and quality issues mitigation. ### Qualifications - Bachelor degree in Electrical Engineering. with a minimum of 12 years of experience OR MS with a minimum of 10 years of experience OR PhD with a minimum of 8 years of experience - Minimum of 10 years of experience in developing board level hardware and systems - Demonstrated leader in guiding junior HW engineers. Proven success in taking HW systems from concept to production. Experience in system architecture, SI/PI, power, BM, high speed interfaces, … Experience with schematic capture software Good communication especially in creation of plans and reports. Familiarity with volume manufacturing methods and processes is a plus. Ability to lead and contribute to cross-functional teams, demonstrate good interpersonal skills, be able to operate independently and multiplex your time between many diverse tasks The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Oct 8, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 10 days - Location: San Jose - Pay: $178,500 to $331,500[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Sr-Principal-HW-Design-Engineer-HW-Architect_R55582) ## More jobs at Cadence Design ### [DSP Hardware Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/dac6d4c7af4a4d5a5b7d/) San Jose ### [Lead Analog IC Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/41a337490e8e814bb762/) San Jose ### [Lead Red Hat Linux Architect](https://jobs.opennash.com/companies/cadence-design/jobs/4304555936c674ce4b12/) San Jose ### [Mixed-Signal, Sr Principal Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/586c1eb9a71bb1464921/) San Jose ### [Principal AE, Serdes Design IP](https://jobs.opennash.com/companies/cadence-design/jobs/565e79527e05b7a29b5f/) San Jose ## Similar jobs at other companies ### [FPGA Emulation Engineer (Staff/ Senior Staff/ Principal)](https://jobs.opennash.com/companies/qualcomm/jobs/c3c5393500f6520ede77/) Qualcomm · Ho Chi Minh, Hồ Chí Minh, Vietnam ### [Emulation Engineer - Sr/Lead/Staff Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/f6ba1fa4b200210b9a1e/) Qualcomm · Hyderabad, Telangāna, India ### [Senior Applications Engineer - Emulation](https://jobs.opennash.com/companies/siemens/jobs/4a9890b196501d13484c/) Siemens ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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