[Skip to main content](#main-content)

[OpenNash Jobs](https://jobs.opennash.com/)
[Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/)

Cadence Design

# Sr. Principal Design Engineer

Senior individual contributor Design 

Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/NOIDA-01/Sr-Principal-Design-Engineer_R55559)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Sr. Principal Design Engineer

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Role Overview & Objective We are looking for a motivated SRAM Circuit Design Engineer to join our semiconductor engineering team developing circuits and SRAM/Register File for low power, low voltage and high performance.

This role is ideal for candidates who are passionate about memory design, characterization methodologies, and physical verification, and who are eager to build a strong foundation in VLSI memory development.

### Key Responsibilities
- Circuit Design & Optimization: Build full-custom or compiler-based SRAM macros, sense amplifiers, and self-timed circuits.

### Simulation & Characterization

Run SPICE simulations to analyze timing, power, and Static Noise Margin (SNM) across process corners.

### Layout Supervision

Direct physical design and layout teams to handle process variability and FinFET manufacturing rules.

### Silicon Validation & Debug

Support post-silicon testing and troubleshooting hardware failures

### Required Qualifications & Experience
- Education: B.Tech/M.Tech in Electrical Engineering, VLSI, or Microelectronics.

### Experience

Typically ranges from 6 to 18 years depending on whether the role is entry/mid-level or a senior lead/architect position.

### Core Knowledge

Deep understanding of CMOS device physics, transistor sizing, and memory cell stability.

### Tools

Proficiency in EDA software like Cadence Virtuoso or SPICE simulators.

### Scripting

Ability to use Python or Perl for workflow automation and data analysis
- Behavioral & Soft Skills Strong analytical and problem-solving skills. High attention to detail. Ability to collaborate cross-functionally with circuit designers, architecture teams, and CAD engineers.

We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 7 days[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/NOIDA-01/Sr-Principal-Design-Engineer_R55559)

## More jobs at Cadence Design

### [AI Intern - Technical Communications (System Design Analysis Group)](https://jobs.opennash.com/companies/cadence-design/jobs/3fd4e202987c9263bc42/)

### [Analog Design Engineer II](https://jobs.opennash.com/companies/cadence-design/jobs/32273bb1256173e417c3/)

Nanjing

### [Analog/Mixed-Signal IC Design Co-Op/Intern (Summer 2026) / Stage/Co-Op en Conception de CI Analogiques/Signal Mixte (Été 2026)](https://jobs.opennash.com/companies/cadence-design/jobs/24328000d0824efdc101/)

MOUNT-ROYAL

### [Application Engineer I: Physical Design - Synthesis and Digital Implementation](https://jobs.opennash.com/companies/cadence-design/jobs/4e2269ad4ab1e223170f/)

Belo Horizonte

### [Application Engineer II: Analog IC Design and Simulation](https://jobs.opennash.com/companies/cadence-design/jobs/3973b64c3a637ee148b9/)

Belo Horizonte

## Similar jobs at other companies

### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/)

Sandisk 

### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/)

Sandisk 

### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/)

Microsoft · India, Karnataka, Bangalore

### [RISCV CPU Design Verification Principal Manager/ Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/312f1b332fbcaab058e8/)

Qualcomm · Bangalore, India

### [Principal Engineer/Senior Staff Engineer- CPU Software & Hardware Co-Design Engineer (ML Systems)](https://jobs.opennash.com/companies/qualcomm/jobs/1fd1ae44127e47ec80dd/)

Qualcomm · Bangalore, India

OpenNash lists jobs from employers’ own careers sites and does not handle applications.
Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)
