[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · Hyderabad # Lead Design Engineer Hyderabad Manager or lead Design Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/HYDERABAD/Lead-Design-Engineer_R52796) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Lead Design Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Profile Role Title Lead Design Engineer, SoC / Subsystem / IP Design Experience 4to 18 years Qualification:BE/BTECH/ME/MTECH ### Role Summary Lead the design and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure. Own micro-architecture, RTL development, quality reviews, and cross-functional coordination with verification, physical design, DFT, firmware, and architecture teams. Drive high-quality, reusable, and implementation-ready designs aligned to power, performance, and area targets. ### Key Responsibilities Own end-to-end RTL design and development of SoC, subsystem, and IP blocks. Translate architecture and product requirements into detailed micro-architecture and implementation plans. Develop high-quality RTL in Verilog/SystemVerilog with focus on correctness, reusability, and scalability. Lead design of key blocks such as interconnects, controllers, bridges, memory interfaces, datapaths, and control logic. Drive block-level and subsystem-level design integration and resolve interface, timing, and functionality issues. Work closely with verification teams to review test plans, support debug, and ensure design quality and closure. Collaborate with physical design teams on timing, power, area, clocking, reset, and synthesis constraints. Support DFT, CDC, RDC, lint, low-power, and formal checks, and drive closure on design issues. Review specifications, micro-architecture documents, RTL, and design changes to ensure robustness and quality. Analyze and resolve design bugs found in simulation, emulation, silicon bring-up, or customer use cases. Mentor junior engineers and provide technical direction on coding practices, design quality, and methodology. Contribute to design methodology improvements, reusable IP development, and automation initiatives. ### Required Skills and Qualifications Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or related field. 10 to 14 years of experience in digital design with strong exposure to IP, subsystem, and SoC development. Strong expertise in RTL design using Verilog/SystemVerilog. Solid understanding of digital design fundamentals, FSMs, pipelines, arbitration, buffering, and clock/reset design. Strong experience in micro-architecture definition and hardware implementation. Good understanding of AMBA protocols such as AXI, AHB, and APB. Experience in designing interconnects, bus fabrics, DMA, memory-mapped peripherals, control/data path logic, or protocol bridges. Strong debugging skills for simulation, synthesis, and integration issues. Familiarity with lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power design flows. Exposure to power, performance, and area optimization techniques. Scripting experience in Python, Perl, Tcl, or Shell for automation and productivity improvements. Strong communication and cross-functional collaboration skills. ### Preferred Skills Experience with PCIe, DDR, NoC, cache/coherency, security, or safety-related designs. Exposure to low-power design methodologies including UPF/CPF. Experience with formal verification support and silicon debug. Experience leading small design teams or owning major subsystems in large SoC programs. ### Key Competencies RTL and micro-architecture ownership SoC and subsystem integration Technical leadership Problem solving and debug Quality and design closure focus We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: Hyderabad[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/HYDERABAD/Lead-Design-Engineer_R52796) ## More jobs at Cadence Design ### [Design Engineer II](https://jobs.opennash.com/companies/cadence-design/jobs/7f6f654f9c4f7fe714d5/) Hyderabad ### [Design engineering Architect](https://jobs.opennash.com/companies/cadence-design/jobs/563be5a022b35f0476a9/) Hyderabad ### [Principal Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/762c01df18624c36410d/) Hyderabad ## Similar jobs at other companies ### [Senior Staff Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering](https://jobs.opennash.com/companies/sandisk/jobs/9c9c9ee8de475c168163/) Sandisk ### [Senior Technologist Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering](https://jobs.opennash.com/companies/sandisk/jobs/04c89e21c7a143aa3d7b/) Sandisk ### [Staff / Senior Staff Engineer Digital Design (RTL Design)](https://jobs.opennash.com/companies/infineon-technologies/jobs/bcdb3b7a61b92eede1d2/) Infineon Technologies · Singapore ### [Electrical Design Engineer - Substation Bengaluru, Karnataka Bengaluru, Karnataka ENGINEERING / DESIGN STUDIES / METHODS ENGINEERING / DESIGN STUDIES / METHODS Permanent](https://jobs.opennash.com/companies/vinci/jobs/226b30542f183b716535/) VINCI · Bengaluru, Karnataka ### [Senior Design Engineer - UGC Scotland Gate, England Scotland Gate, England ENGINEERING / DESIGN STUDIES / METHODS ENGINEERING / DESIGN STUDIES / METHODS](https://jobs.opennash.com/companies/vinci/jobs/e05c4ba864beb3623d58/) VINCI · Scotland Gate, England OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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