[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · San Jose # Sr. Principal Product Engineer San Jose Senior individual contributor $161,000 to $299,000 Operations Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Sr-Principal-Product-Engineer_R56322) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Sr. Principal Product Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This Senior Principal Product Engineer is a technical leader on the Voltus product engineering team, working on Cadence’s power noise and reliability analysis platform. The role sits between strategic customers/foundries, Applications, and R&D, and is accountable for turning the hardest IR/EM, PDN, and electrothermal signoff requirements into product and flow solutions. Key responsibilities Serve as the primary technical interface to R&D for Voltus, driving product requirements, priorities, and methodology for strategic foundry and customer programs. ### Lead Voltus enablement for advanced-node IR/EM signoff flow/techfile/PDK readiness, reference flows, qualification, benchmarking, and production deployment. Own resolution of complex customer issues spanning static/dynamic IR, EM, low-power / multi-voltage domains, hierarchical and full-chip signoff, and related timing/stack-die interactions. Define and validate foundry-aligned power integrity and EM modeling assumptions; partner with PDK, extraction, and signoff teams on advanced-node and 3DIC readiness. Influence product roadmap (including AI-driven IR mitigation, 3DIC, and electrothermal co-analysis) based on foundry and customer gaps. Mentor Lead/Principal PEs and AEs; set debug standards, deployment practices, and issue-tracking discipline for the account/foundry program. Work effectively with customers, Cadence field, Marketing, and R&D across geographies; present findings and recommendations to customer and internal leadership. Minimum qualifications Bachelor’s in Electrical / Electronics / VLSI Engineering with 10+ years of related experience, or MS with 8+ years, or PhD with 6+ years. Deep hands-on experience with industry-standard IR/EM (EMIR) and PDN analysis tools and digital physical implementation / signoff flows. Strong background in CMOS/digital design, power IR-drop analysis, circuit analysis, and low-power / multi-power-domain chip power-integrity signoff. Proven ability to separate critical issues from noise, debug large SoC/PDN problems, and close the loop from customer requirement to R&D fix to deployment. Scripting in Tcl and Python; strong written, verbal, and presentation skills with customer and executive audiences. Preferred Direct experience with Voltus and adjacent Cadence digital signoff/implementation tools (Integrity, Tempus, Innovus, Quantus/QRC). 3DIC / chiplet, electrothermal, and advanced FinFET or GAA node experience. Prior technical leadership of PE/AE teams or of a strategic account/foundry program. The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 7 days - Location: San Jose - Pay: $161,000 to $299,000[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Sr-Principal-Product-Engineer_R56322) ## More jobs at Cadence Design ### [ATE Test Engineering Architect](https://jobs.opennash.com/companies/cadence-design/jobs/9e10fb091249050ec22d/) San Jose ### [Applied ML – Functional Verification Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/fe0a7f82610053d8d221/) San Jose ### [CST Application Engineer - Systems/ATX](https://jobs.opennash.com/companies/cadence-design/jobs/d37fcf59ed841608a74e/) San Jose ### [CST Application Engineer Intern - Physical Systems](https://jobs.opennash.com/companies/cadence-design/jobs/03fe481b63792e905870/) San Jose ## Similar jobs at other companies ### [Principal Engineer, Product Development Engineering](https://jobs.opennash.com/companies/sandisk/jobs/6d7cd6c9e5d306dc30ff/) Sandisk ### [Senior/Principal Product Systems Engineer](https://jobs.opennash.com/companies/microsoft/jobs/c8554f8332bf5fab3098/) Microsoft · United Kingdom, Cambridgeshire, Cambridge ### [Associate Principal Product Engineer(P&R)](https://jobs.opennash.com/companies/siemens/jobs/f111b547b44902c4be1d/) Siemens ### [Principal Product Manager](https://jobs.opennash.com/companies/target/jobs/977b8c84ac0228553460/) Target · Bangalore, India ### [Principal Product Manager](https://jobs.opennash.com/companies/microsoft/jobs/02eaa2a54385ee71b5ee/) Microsoft · India, Karnataka, Bangalore OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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