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Cadence Design · Shanghai

# Principal Product Engineer - DIP

Shanghai Senior individual contributor Operations 

Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Principal-Product-Engineer---DIP_R55731)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Principal Product Engineer - DIP

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

### Key Responsibilities

Technical Support & Case Management: Act as the primary interface for technical issues, driving resolution for complex subsystem application or implementation problems. This includes monitoring case management systems like Salesforce (SFDC) and Jira.

### IP Integration & Validation

Support Pre-Silicon integration, post-silicon bring-up, and verification of PHY and controller SoC integration. Conduct RTL and gate-level simulations to ensure functionality and assist with timing closure.

### Customer Engagement

Proactively engage with customers to identify potential issues, prioritize critical technical problems, and manage escalations, ensuring high satisfaction.

### Technical Leadership

Develop comprehensive knowledge bases, document product limitations, and provide feedback to internal Product Engineering and R&D teams for continuous improvement.

### Guidance & Training

Create and deliver technical training, seminars, and documentation to support customer success and adoption of best practices.

### Required Qualifications

Experience: Requires 8+ years of experience in verification and design, specifically with IP development.

### Technical Expertise

Strong background in digital electronics, Verilog/SystemVerilog, and UVM methodology.

### Protocol Knowledge

Practical knowledge of memory or communication interface IP protocols such as MIPI (CSI2/DSI/I3C/PHY), PCI Express, DDR, LPDDR, HBM, or USB.

### Skills

Excellent debugging skills, ability to handle complex problems, and proficiency in scripting languages (TCL, Perl, or Python).

### Education

Bachelor’s or Master’s in Electronics or Electrical Engineering.

### Preferred Skills

Experience with Cadence-specific tools, EDA workflows, or similar IP design platforms.

### Core Competencies

Strong communication and presentation skills, capable of influencing both internal teams and customer stakeholders. Proactive and collaborative approach, able to work across global, cross-functional teams. Strategic thinking to drive product roadmap improvements based on user feedback. Fluent spoken English We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Oct 11, 2026
- Last checked: Oct 18, 2026
- Listed for: 7 days
- Location: Shanghai[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Principal-Product-Engineer---DIP_R55731)

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