[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · Shanghai # Sr Principal Verification Engineer Shanghai Senior individual contributor Operations Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Sr-Principal-Verification-Engineer_R54748) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Sr Principal Verification Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. ### Qualifications Minimal qualification requires BS/MS degree EE or CS with [ 5-7+ years (T4) ] of experience in relevant experience. As a [Principal Verification Engineer (T4) ] you will be responsible for scheduling, designing, developing, and supporting UVM-based verification environments, processes, and methodologies for IP models of system level memory such as SDRAM ( LPDDRx, DDRx, HBMx), DFI PHY, UFS, and complex storage memory models for use on hardware-based verification products. - Must analyze customer & vendor protocol requirements and execute on highly complex verification projects from requirements through delivery to post-delivery support. - Must analyze product-wide feature requirements and execute on their verification. - Must integrate additional related tools and processes—including coverage, reporting, and regressing—to build a robust team-level verification structure and competence. ### Additional responsibilities include the following - Researching tools, languages, methodologies and prototype processes to enhance product verification as well as to demonstrate product quality. - Updating, enhancing, maintaining, and supporting existing system level UVM test environments for memory model products. - Supporting product (IP Library) regression, OS compliance, process automation, and product release preparation as needed. ### Job Responsibilities & Skills [Principal Verification Engineer (T4) ] - Candidate must be an Electrical, Electronics or Computer Science Engineer with expert understanding of HDLs and HVLs such as Verilog and SystemVerilog. - Solid experience in simulation/emulation using these languages. He/ she should have expert working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/verification problems using these tools. - Deep experience with UVM, SystemVerilog, and C++. - Must have solid, deep experience on multiple protocols such as UFS Unipro and MPHY, SDRAM, Ethernet, PCIe, USB3/4, MIPI etc - Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. - Experience with Functional Verification of complex protocol-based blocks—e.g. UFS / Unipro / MPHY verification—with a Hardware Verification Language (HVL) like SystemVerilog. - Experience designing and implementing complex functional verification environments is required. - Experience in process automation with scripting is required. Behavioral skills required. - Possess very strong English verbal and written skills. - Ability to establish close, collaborative working relationships with team colleagues, peers, customers, vendors, and management. - Likewise, the ability to execute with strong individual and independent R&D skills. - Motivation and capacity to mentor less experienced engineers and to participate in cross-functional projects. - Explore what’s possible to complete a committed job while maintaining high product quality. - Work effectively across functions and geographies. - Participate in team processes; evaluate and recommend process improvements. ### Strongly recommended - Verification experience using Cadence simulation and/or emulation products is highly desired. - Experience in memory sub-system or controller verification and operation is strongly recommended. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 18, 2026 - Listed for: 100 days - Location: Shanghai[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Sr-Principal-Verification-Engineer_R54748) ## More jobs at Cadence Design ### [Customer Engagement Engineer - Pegasus](https://jobs.opennash.com/companies/cadence-design/jobs/5c38ad74d23dae5abff7/) Shanghai ### [Intern-Product validation engineer](https://jobs.opennash.com/companies/cadence-design/jobs/e0983128beb02490ffdf/) Shanghai ### [Lead Application Engineer - Actran](https://jobs.opennash.com/companies/cadence-design/jobs/e24dcd40e7758765fe2c/) Shanghai ### [Lead Application Engineer - Adams](https://jobs.opennash.com/companies/cadence-design/jobs/3e37f37f3ba4085c994e/) Shanghai ### [Lead Application Engineer - Forming Suite](https://jobs.opennash.com/companies/cadence-design/jobs/ee85e889384cdf969a08/) Shanghai ## Similar jobs at other companies ### [SOC Verification Principal Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/287d6238eb14a245feeb/) Qualcomm · Bangalore, India ### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/) Microsoft · India, Karnataka, Bangalore ### [Principal SOC Performance Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/4978befbe1d83beb7e57/) Microsoft · India, Karnataka, Bangalore ### [RISCV CPU Design Verification Principal Manager/ Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/312f1b332fbcaab058e8/) Qualcomm · Bangalore, India ### [Principal Engineer, Firmware Verification Engineering](https://jobs.opennash.com/companies/sandisk/jobs/6e34b15789e0b69b44f1/) Sandisk OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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