[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · AUSTIN # Principal Design Engineer AUSTIN Senior individual contributor Design Listed on Cadence Design’s official careers site. Posted October 2, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/AUSTIN/Principal-Design-Engineer_R56619) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Principal Design Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. ### Required Qualifications B.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field 8–10 years of hands-on DV experience in semiconductor/ASIC/SoC companies Deep expertise in SystemVerilog and UVM (Universal Verification Methodology) - Strong understanding of digital design fundamentals — RTL, timing, clocking, resets Experience with industry-standard simulators: Xcelium, VCS, Questa - Proficiency in coverage-driven verification — functional, code, and toggle coverage Hands-on experience with formal verification tools and flows Experience with bus protocols such as AXI, AHB, APB, PCIe, DDR, or similar - Strong debug skills — waveform analysis (Verisium, SimVision) - Familiarity with low-power verification (UPF/CPF) and gls/power-aware gls simulation ### Core Responsibilities Strategy and Architecture Verification Planning: Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure. ### Testbench Architecture Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers. ### Feature Extraction Analyze architectural specifications to identify critical features and corner cases that require rigorous testing. ### Execution and Technical Leadership Customer Interaction Technically lead DV execution of small to mid-sized customer ASIC projects. Handle customer interactions. Convert high level customer requirements into DV execution plan. ### Development Write complex test cases and sequences to achieve high functional coverage. ### Debug Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes. ### Constraint Random Testing Implement constrained-random stimulus generation to explore the design space beyond directed tests. ### Formal Verification Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss. ### Metric Management Coverage Analysis Monitor and analyze functional and code coverage metrics. ### Gate-Level Simulation (GLS) Oversee simulations on the synthesized netlist to verify timing and reset behavior. ### Sign-off Define the "definition of done" and provide final technical approval for the verification phase. ### Soft Skills and Leadership Mentorship Guiding junior engineers on coding standards and debugging techniques. ### Cross-functional Collaboration Acting as the primary technical point of contact between the design, architecture, and emulation teams. ### Project Management Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Oct 2, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 16 days - Location: AUSTIN[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/AUSTIN/Principal-Design-Engineer_R56619) ## More jobs at Cadence Design ### [DFT Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/f2f8b52a9bff821f7f50/) AUSTIN ### [Design Engineer II](https://jobs.opennash.com/companies/cadence-design/jobs/22527f087f7464e5e115/) AUSTIN ### [Group Director, Design Engineering - Front End](https://jobs.opennash.com/companies/cadence-design/jobs/2745c57cc037325074f2/) AUSTIN ### [Lead Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/a0b4b9f419b350df76c0/) AUSTIN ## Similar jobs at other companies ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk ### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/) Sandisk ### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/) Microsoft · India, Karnataka, Bangalore ### [RISCV CPU Design Verification Principal Manager/ Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/312f1b332fbcaab058e8/) Qualcomm · Bangalore, India ### [Principal Engineer/Senior Staff Engineer- CPU Software & Hardware Co-Design Engineer (ML Systems)](https://jobs.opennash.com/companies/qualcomm/jobs/1fd1ae44127e47ec80dd/) Qualcomm · Bangalore, India OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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