[Skip to main content](#main-content)

[OpenNash Jobs](https://jobs.opennash.com/)
[Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/)

Cadence Design · Multiple locations

# Sr Principal Design Engineer

Multiple locations Senior individual contributor Design 

Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there.
[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Engineering-Architect_R45339)

[OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Sr Principal Design Engineer

## Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

### Position Description

RTL Design Engineer for DDR Memory Controller IP development team. The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4. The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines.

### Position Requirements

BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development. RTL Design using Verilog is a must. System Verilog experience and experience with UVM based environment usage / debugging is required. AXI3/4 experience is desired. DDR Memory controller and protocol experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.

Prior experience in IP development teams would be an added advantage. We’re doing work that matters. Help us solve what others can’t.

## At a glance
- Posted by the employer: Not stated
- First seen by OpenNash: Jul 10, 2026
- Last checked: Oct 18, 2026
- Listed for: 100 days
- Location: Multiple locations[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Design-Engineering-Architect_R45339)

## More jobs at Cadence Design

### [Principal Analog IC Designer](https://jobs.opennash.com/companies/cadence-design/jobs/2ca49f73e6796cbe4765/)

### [CST Application Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/f1f484aa512f301fabe2/)

### [IT - Staff Network Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/4922237439e0c51bdae7/)

### [AI Intern - Technical Communications (System Design Analysis Group)](https://jobs.opennash.com/companies/cadence-design/jobs/3fd4e202987c9263bc42/)

### [Analog Design Engineer II](https://jobs.opennash.com/companies/cadence-design/jobs/32273bb1256173e417c3/)

Nanjing

## Similar jobs at other companies

### [Principal High Speed Clocking Design Engineer](https://jobs.opennash.com/companies/monolithic-power-systems/jobs/82456013863f6ecbab12/)

Monolithic Power Systems 

### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/)

Sandisk 

### [Principal Mechanical Design Engineer](https://jobs.opennash.com/companies/bouygues/jobs/fcb3d746f54a76b38df1/)

Bouygues · MOTHERWELL, United Kingdom

### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/)

Sandisk 

### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/)

Microsoft · India, Karnataka, Bangalore

OpenNash lists jobs from employers’ own careers sites and does not handle applications.
Dates come from the employer where stated; “first seen” and “last checked” are our own observations.

OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)