[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · San Jose # Senior Principal Design Engineer-Palladium & Protium Customer Enablement & Solutions San Jose Senior individual contributor $154,000 to $286,000 Design Listed on Cadence Design’s official careers site. Posted October 8, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Sr-Principal-Design-Engineer_R55242-1) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Senior Principal Design Engineer-Palladium & Protium Customer Enablement & Solutions ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our North America Palladium and Protium HW Development team and help shape the future of system-level chip design verification. In this highly visible, customer-facing role, you will work directly with industry-leading semiconductor and systems companies to develop and deploy Cadence’s market-leading hardware emulation and FPGA prototyping platforms. You will bridge the gap between customers, Applications Engineering (AE), Product Engineering (PE), and R&D — develop impactful customer solutions, delivering deep R&D technical support, and pioneering innovative verification methodologies to solve our customers’ most complex architectural and high-Speed Protocol challenges. ### Key Responsibilities Customer Enablement & Solutions: Collaborate with frontline engineering teams and customers to develop, deploy, productize, and optimize advanced protocol solutions on Palladium and Protium platforms. ### Requirements & Feature Development Define and develop customer-specific emulation and prototyping requirements, focusing heavily on leading edge high-speed interfaces and memory protocols (e.g., PCIe, CXL). ### Advanced Solutions Engineering Drive the development of advanced acceleration FW + FPGA system solutions, establish robust verification methodologies, and support the operation and maintenance of Cadence emulation tools. ### Root-Cause Debugging Triage and resolve complex, systemic issues across the hardware/software boundary, optimizing driver behavior, protocol compliance, and overall system stability. ### Evaluations & Benchmarking Lead technical evaluations and develop high-performance benchmarks to demonstrate the competitive advantages of Cadence hardware platforms. ### Technical Presentation Create and deliver impactful technical presentations, white papers, and product demonstrations for existing and prospective customers. ### What You’ll Need BS with a minimum of 10 years of experience or MS with a minimum of 7 years of experience - Strong fundamentals in digital design, computer architecture, and system‑level verification Have deep technical knowledge in a few of; Simulation (Advanced Testbench), Emulation (TBA & ICE) & FPGA Prototyping Experience with hardware description languages (SystemVerilog/Verilog) and/or C/C++ Understanding of standard interconnect or IO protocols used in modern chip designs Good debugging skills using waveforms, logs, and protocol analyzers - Ability to work across hardware and software boundaries. Excellent communication, and interpersonal skills, ability to work in an international environment The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Oct 8, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 10 days - Location: San Jose - Pay: $154,000 to $286,000[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Sr-Principal-Design-Engineer_R55242-1) ## More jobs at Cadence Design ### [DSP Hardware Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/dac6d4c7af4a4d5a5b7d/) San Jose ### [Lead Analog IC Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/41a337490e8e814bb762/) San Jose ### [Lead Red Hat Linux Architect](https://jobs.opennash.com/companies/cadence-design/jobs/4304555936c674ce4b12/) San Jose ### [Mixed-Signal, Sr Principal Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/586c1eb9a71bb1464921/) San Jose ### [Principal AE, Serdes Design IP](https://jobs.opennash.com/companies/cadence-design/jobs/565e79527e05b7a29b5f/) San Jose ## Similar jobs at other companies ### [Beauty Advisor - MAC Palladium - On Call / Freelance - Palladium, Praha](https://jobs.opennash.com/companies/estee-lauder/jobs/accea4474747066d40b4/) The Estée Lauder Companies · Prague, PR, CZ, Czech Republic ### [Principal VLSI Design Engineer, Datapath Design Expert](https://jobs.opennash.com/companies/sandisk/jobs/29d656d770125294c246/) Sandisk ### [Principal Mechanical Design Engineer](https://jobs.opennash.com/companies/bouygues/jobs/fcb3d746f54a76b38df1/) Bouygues · MOTHERWELL, United Kingdom ### [Principal Mask Design Engineer](https://jobs.opennash.com/companies/sandisk/jobs/82554c377b8c4f46d335/) Sandisk ### [Principal Formal Design Verification Engineer](https://jobs.opennash.com/companies/microsoft/jobs/77157c255f58687bb52b/) Microsoft · India, Karnataka, Bangalore OpenNash lists jobs from employers’ own careers sites and does not handle applications. Dates come from the employer where stated; “first seen” and “last checked” are our own observations. OpenNash Jobs · Official listings with dates and links to the employer. [Weekly hiring report](/reports/hiring/) · [Methodology](/methodology/)