[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design # Lead Design Engineer Manager or lead Design Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/HYDERABAD-04/Lead-Design-Engineer_R46047) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Lead Design Engineer ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. ### Job Description To develop & integrate foundry rule decks & technology files to support PDKs by using foundry provided process design kits as a starting point. PDK QA, verification and release methodology for decks and specialized setups including track patterns to aid in layout. Responsible for physical verification methodology, including installation, development, qualification, automation, and support – To develop scripts to automate LVS, DRC, RM,IR and Parasitic Extraction flows. And to support layout teams in verification flow issues. Ensuring QA of the integrated PDK’s with the custom design environment Add sub scripts to improve efficiency on QA process with adequate coverage. General tool usage support – real-time support of all tools, creating bug workarounds and filing CCRs with R&D Responsible for rule deck development - to implement process design rules into physical verification rules decks and QC for the rule decks. Responsible for interfacing with the design teams and foundry team to develop and verify our PDKs. Develop, own and maintain an automation frame work for efficiency improvement perspective for the design environment. ### Position Requirements Bachelor’s Degree in Electrical/Electronic Engineering or equivalent. 4-7 years of Work experience in PDK development and CAD enablement. Expertise in Cadence Python, SKILL, Perl programming languages. Knowledge of deep sub-micron CMOS processes, device physics and layout design. Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors. Experience in developing PDK device library components and definitions including SKILL parameterized cells (Pcell), symbols, CDF, callbacks, simulation/netlisting. Experience with physical verification tools for DRC, LVS and parasitic extraction, Cadence PVS, Assura is a plus. Working knowledge of revision control software (Git, sos, Subversion, Synchronicity, etc) Understanding on Pcell creation and enhancements to pcell parameters, device call backs etc is a plus Excellent technical problem solving skills. Excellent communication and presentation skills. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 18, 2026 - Listed for: 100 days[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/HYDERABAD-04/Lead-Design-Engineer_R46047) ## More jobs at Cadence Design ### [AI Intern - Technical Communications (System Design Analysis Group)](https://jobs.opennash.com/companies/cadence-design/jobs/3fd4e202987c9263bc42/) ### [Analog Design Engineer II](https://jobs.opennash.com/companies/cadence-design/jobs/32273bb1256173e417c3/) Nanjing ### [Analog/Mixed-Signal IC Design Co-Op/Intern (Summer 2026) / Stage/Co-Op en Conception de CI Analogiques/Signal Mixte (Été 2026)](https://jobs.opennash.com/companies/cadence-design/jobs/24328000d0824efdc101/) MOUNT-ROYAL ### [Application Engineer I: Physical Design - Synthesis and Digital Implementation](https://jobs.opennash.com/companies/cadence-design/jobs/4e2269ad4ab1e223170f/) Belo Horizonte ### [Application Engineer II: Analog IC Design and Simulation](https://jobs.opennash.com/companies/cadence-design/jobs/3973b64c3a637ee148b9/) Belo Horizonte ## Similar jobs at other companies ### [Senior Staff Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering](https://jobs.opennash.com/companies/sandisk/jobs/9c9c9ee8de475c168163/) Sandisk ### [Senior Technologist Datapath Design Engineer and Circuit Design Engineer, VLSI Design Engineering](https://jobs.opennash.com/companies/sandisk/jobs/04c89e21c7a143aa3d7b/) Sandisk ### [Staff / Senior Staff Engineer Digital Design (RTL Design)](https://jobs.opennash.com/companies/infineon-technologies/jobs/bcdb3b7a61b92eede1d2/) Infineon Technologies · Singapore ### [Electrical Design Engineer - Substation Bengaluru, Karnataka Bengaluru, Karnataka ENGINEERING / DESIGN STUDIES / METHODS ENGINEERING / DESIGN STUDIES / METHODS Permanent](https://jobs.opennash.com/companies/vinci/jobs/226b30542f183b716535/) VINCI · Bengaluru, Karnataka ### [Senior Design Engineer - UGC Scotland Gate, England Scotland Gate, England ENGINEERING / DESIGN STUDIES / METHODS ENGINEERING / DESIGN STUDIES / METHODS](https://jobs.opennash.com/companies/vinci/jobs/e05c4ba864beb3623d58/) VINCI · Scotland Gate, England OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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