[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Cadence Design jobs](https://jobs.opennash.com/companies/cadence-design/) · [Search jobs](/search/) Cadence Design · Multiple locations # Lead Software Engineer - Compiler/LLVM Multiple locations Manager or lead Software Engineering Listed on Cadence Design’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/CORK-01/Lead-Software-Engineer_R54825) [OpenNash Jobs](https://jobs.opennash.com/) / [Cadence Design](https://jobs.opennash.com/companies/cadence-design/) / Lead Software Engineer - Compiler/LLVM ## Job description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. ### Job Title Lead Software Engineer – Compiler/LLVM Location: Cork, Ireland or Belo Horizonte, Brazil Reports to: Sr Software Architect Job Overview: Tensilica, a Cadence company, delivers configurable processor IP and DSP solutions powering AI, vision, audio, and communications workloads. Its Xtensa® architecture enables highly optimized, domain-specific designs with industry-leading performance and efficiency. The C Compiler team builds the toolchain that unlocks this performance. Working on LLVM-based compilers for Xtensa processors, the team drives code generation, architecture-aware optimizations, and real-world workload performance. In close partnership with hardware teams, they enable new capabilities and deliver production-grade tools used by leading semiconductor and systems companies. ### Responsibilities - Design and implement compiler optimisations and features for Xtensa processors - Drive improvements in code generation, performance tuning, and architecture enablement across the toolchain - Partner closely with hardware and architecture teams on new ISA features and capabilities - Analyse and optimise real‑world workloads, including AI, DSP, and vision use cases - Provide technical mentorship to junior engineers and contribute to the team’s technical direction and best practices Requirements: Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field (or equivalent practical experience) Typically - 4+ years of experience in compiler development or low‑level systems software (academic or industry experience considered) Strong C/C++ programming skills with solid debugging and problem‑solving expertise Good understanding of compiler internals (LLVM, GCC, or similar frameworks) - Strong foundation in computer architecture and performance optimisation Nice to Have: Experience with DSPs, AI/ML workloads, or embedded systems Hands‑on experience with LLVM or GCC backends and optimisation passes Experience working close to hardware teams or enabling new processor architectures - Check what we can offer you: Competitive salary 25 days holiday per year Private Medical and Dental plans, Income Protection and Life Insurance Group Personal Pension Plan Cycle to work scheme and gym subsidy 5 days paid time to volunteer to give back to our communities Employee Stock Purchase Plan The opportunity to work for a Great - Place to Work© & Fortune 100 organization Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. We’re doing work that matters. Help us solve what others can’t. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 18, 2026 - Listed for: 100 days - Location: Multiple locations[Apply on Cadence Design’s careers site →](https://cadence.wd1.myworkdayjobs.com/External_Careers/job/CORK-01/Lead-Software-Engineer_R54825) ## More jobs at Cadence Design ### [CFD software enginner](https://jobs.opennash.com/companies/cadence-design/jobs/45522e048d5c4fbd3db4/) ### [Firmware Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/6461962fd298a6cdbd40/) ### [IT- Staff Software Security Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/0a9248fbc46a4c09c84e/) ### [Ingénieur en conception de micrologiciel - Firmware Design Engineer](https://jobs.opennash.com/companies/cadence-design/jobs/67d0a1a418ccc702ea2c/) ## Similar jobs at other companies ### [Senior Compiler Optimization Engineer – LLVM](https://jobs.opennash.com/companies/nvidia/jobs/ea1ab00806f2fbda2951/) NVIDIA ### [Software Engineering Intern, Compiler Verification - Spring 2027](https://jobs.opennash.com/companies/nvidia/jobs/cd05b0f4da8d529fc68d/) NVIDIA ### [Principal AI Compiler Engineer](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/cda97783183d505f3d9c/) NXP Semiconductors ### [Staff Software Engineer](https://jobs.opennash.com/companies/alphabet/jobs/0642bb3244ad0f65673e/) Alphabet ### [[WiFi] Software Engineer / Senior Software Engineer / Principal Software Engineer](https://jobs.opennash.com/companies/nxp-semiconductors/jobs/cf1fcd7ef641613787b8/) NXP Semiconductors OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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