[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Broadcom · USA # Principal Physical Design Engineer USA Full-time Senior individual contributor USD 143,800.00 To USD 230,000.00 Design Listed on Broadcom’s official careers site. Posted October 30, 2026. Check that it is still open and apply there. [Apply on Broadcom’s careers site →](https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-CA-San-Jose-Innovation-Drive/Principal-Physical-Design-Engineer_R027512) [OpenNash Jobs](https://jobs.opennash.com/) / [Broadcom](https://jobs.opennash.com/companies/broadcom/) / Principal Physical Design Engineer ## Job description ### Please Note 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. ### Job Description Principal Physical Design Engineer — ASIC Products Division (APD) ### Location San Jose, CA Position Type: Full-Time Who We Are — Physical Design Team in APD Broadcom’s ASIC Products Division (APD) is the global leader in custom high-performance silicon solutions. We partner with the world’s most innovative technology companies—spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders—to co-design and manufacture complex, custom ASICs that power the modern digital backbone. The Physical Design team within APD is the world-class execution engine behind the industry's most advanced custom silicon. We push the limits of silicon technology by combining deep architectural expertise, advanced IP, cutting-edge physical design methodologies in 3nm/2nm nodes, and advanced 2.5D/3D chiplet integration to solve the most demanding compute and bandwidth challenges.We transform ultra-complex architectures into fully realized, high-yielding, first-pass silicon success. What Defines Our Physical Design Team Pioneering First-Pass Silicon in 3nm/2nm: Our team consistently pushes the boundary of physics, taking the largest and most complex die sizes from floorplan to tapeout on leading-edge foundry nodes (N7, N5, N3, and N2). ### Record-Breaking Scale & Complexity We regularly execute full-chip physical implementation for ultra-large-scale ASICs exceeding tens of billions of transistors, multi-gigahertz clock frequencies, and dense multi-die 2.5D/3D integration (CoWoS, HBM3/4, chiplet architectures). ### Methodology & Flow Leadership We develop and maintain cutting-edge in-house (AI Driven) automation and methodology across different EDA tools, setting the benchmark for signoff quality and turn-around-time (TAT). About the Role Broadcom’s ASIC Products Division (APD) is looking for a Principal Physical Design Engineer to lead physical design implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. In this role, you will drive complex block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across cutting-edge deep sub-micron nodes (N5/N3/N2/A14). ### Key Responsibilities Full-Flow Implementation: Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus Advanced Node Execution: Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced technology nodes (5nm, 3nm, 2nm) using multi-patterning and complex metal stacks. ### Timing & Power Closure Perform multi-corner multi-mode (MCMM) static timing analysis (STA), signal integrity (SI) optimization, and power grid optimization (static/dynamic IR-drop, EM) for signoff using PrimeTime, Voltus, or RedHawk. ### Qualifications & Requirements Education: B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field. ### Experience 12+ years of hands-on physical design experience successfully taping out complex high-frequency, ultra-large-scale networking or AI ASICs. ### Deep Sub-Micron Expertise Direct experience executing tapeouts in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes. ### EDA Tool Mastery High proficiency in major physical design tool flows: P&R: Cadence Innovus Timing/STA: Synopsys PrimeTime or Cadence Tempus Extraction & IR/EM: StarRC / QRC, RedHawk DRC/LVS: Siemens Calibre Automation Skills: Advanced TCL, Python, and Unix shell scripting for flow automation and database manipulation. ### Communication Excellent technical leadership, problem-solving, and cross-functional communication skills. ### Preferred Qualifications Strong background in high-speed clock network implementation (H-tree, mesh, low-power CTS). Experience with power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating). Compensation and Benefits The annual base salary range for this position is USD 143,800.00 To USD 230,000.00 As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. ### Broadcom offers a competitive and comprehensive benefits package Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence. ## At a glance - Posted by the employer: Oct 30, 2026 - First seen by OpenNash: Nov 1, 2026 - Last checked: Nov 1, 2026 - Listed for: 2 days - Location: USA - Employment type: Full-time - Pay: USD 143,800.00 To USD 230,000.00[Apply on Broadcom’s careers site →](https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-CA-San-Jose-Innovation-Drive/Principal-Physical-Design-Engineer_R027512) ## Hiring at Broadcom - Open jobs: 372 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All Broadcom jobs](https://jobs.opennash.com/companies/broadcom/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Broadcom ### [Design Verification Engineer](https://jobs.opennash.com/companies/broadcom/jobs/da418857e3358ca77ed4/) USA ### [Physical Design Engineer](https://jobs.opennash.com/companies/broadcom/jobs/2c614636cef34dfd6fb6/) USA ## Similar jobs at other companies ### [Principal Physical Design Engineer](https://jobs.opennash.com/companies/microsoft/jobs/51d734722c155c72c64f/) Microsoft · United States, North Carolina, Raleigh, Washington, Redmond, Oregon, Hillsboro, Texas, Austin, California, Mountain View ### [Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/dda9e8d7a67c5354a6eb/) Qualcomm · Tijuana, Baja California, Mexico ### [Physical Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/fef9f3f4b5f327e45365/) Qualcomm · Austin, Texas, United States of America ### [Physical Design CAD Engineer](https://jobs.opennash.com/companies/microsoft/jobs/c6f51a8f2a250a28e52f/) Microsoft · United States, Oregon, Hillsboro, California, Mountain View, North Carolina, Raleigh ### [Circuit Design Engineer, Principal](https://jobs.opennash.com/companies/lockheed-martin/jobs/78cd34d8da60b7b89600/) Lockheed Martin · Goleta, CA OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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