[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Broadcom jobs](https://jobs.opennash.com/companies/broadcom/) · [Search jobs](/search/) Broadcom · San Jose, California, USA # Lead ASIC Design Engineer San Jose, California, USA Full-time Manager or lead $143,800 - $230,000 Design Listed on Broadcom’s official careers site. Listed as of October 18, 2026. Check that it is still open and apply there. [Apply on Broadcom’s careers site →](https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-California-San-Jose-1320-Ridder-Park-Drive/Lead-ASIC-Design-Engineer_R026296) [OpenNash Jobs](https://jobs.opennash.com/) / [Broadcom](https://jobs.opennash.com/companies/broadcom/) / Lead ASIC Design Engineer ## Job description ### Please Note 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. ### Job Description We are seeking a hands-on Principal Digital Design Engineer to serve as the Chip Lead for our next-generation silicon projects. In this high-impact role, you will be the primary technical anchor responsible for the top-level architecture, microarchitecture, and full chip integration. You will guide a cross-disciplinary team spanning analog design, physical design, and verification, owning the design outcome end-to-end from early product definition to a successful foundry tape-out. ### Leadership & Strategic Responsibilities Technical Ownership Serve as the central Chip Lead, defining top-level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle. ### Cross-Discipline Alignment Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met. ### Tape-Out Delivery Own and drive the final tape-out sign-off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry. ### Mentorship & Culture Provide technical guidance, code reviews, and architectural mentorship to mid-level and junior engineers on the team. ### Technical Execution Responsibilities RTL Design Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs). ### Timing & Constraint Ownership Drive top-level chip timing constraints ( SDC), define the Clock Domain Crossing ( CDC) strategy, and establish block-level timing budgets for the PD team. ### Front-End Flows Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis ( STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC). ### IP Management Manage the integration of custom internal analog macros, mixed-signal blocks, and third-party soft/hard IP. ### Silicon Validation Collaborate with post-silicon validation and software teams during initial chip bring-up and lab debug phases. ### Required Qualifications Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. ### Experience 12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead. ### RTL Mastery Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles. ### Tool Fluency Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites). ### Silicon Track Record Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies. ### Communication Outstanding documentation and verbal communication skills; this role authors the authoritative architectural and design specifications for the entire project. ### Work Authorization Must have legal authorization to work in the US. Preferred & Bonus Skills Experience with mixed-signal or high-speed PHY-adjacent architectures (e.g., SerDes, PCIe, DDR, or custom interconnects). Familiarity with DFT (Design for Test) planning, including scan insertion, ATPG planning, and boundary scan. Proficiency in scripting ( Python, Tcl, Perl) to automate and streamline front-end design flows. ### Additional Job Description Compensation and Benefits The annual base salary range for this position is $143,800 - $230,000. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. ### Broadcom offers a competitive and comprehensive benefits package Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence. ## At a glance - Posted by the employer: Not stated - First seen by OpenNash: Jul 10, 2026 - Last checked: Oct 18, 2026 - Listed for: 100 days - Location: San Jose, California, USA - Employment type: Full-time - Pay: $143,800 - $230,000[Apply on Broadcom’s careers site →](https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-California-San-Jose-1320-Ridder-Park-Drive/Lead-ASIC-Design-Engineer_R026296) ## More jobs at Broadcom ### [Design Engineer - Flow Development](https://jobs.opennash.com/companies/broadcom/jobs/69cdd1a957a323a1a177/) San Jose, California, USA ### [Design Engineer - Timing Methodology](https://jobs.opennash.com/companies/broadcom/jobs/bb4e0c0760a05a73b399/) San Jose, California, USA ### [High Speed Analog I/O designer](https://jobs.opennash.com/companies/broadcom/jobs/123b8d39c30844f275d4/) San Jose, California, USA ### [IC Verification Engineer](https://jobs.opennash.com/companies/broadcom/jobs/ada91934084af47e7a1f/) San Jose, California, USA ## Similar jobs at other companies ### [ASIC & FPGA Design Engineer - E2](https://jobs.opennash.com/companies/lockheed-martin/jobs/4510ab87f7a931bd10e6/) Lockheed Martin · Liverpool, NY ### [ASIC & FPGA Design Engineer Sr](https://jobs.opennash.com/companies/lockheed-martin/jobs/90d5256c62b52a8fdb0d/) Lockheed Martin · Boulder, CO ### [ASIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/99c4aabaf2f51a99dc1b/) Qualcomm · San Diego, California, United States of America ### [Digital ASIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/208c975103db0801757a/) Qualcomm · San Diego, California, United States of America ### [Sr. ASIC Design Engineer, Blink/Ring ASIC Team](https://jobs.opennash.com/companies/amazon/jobs/bbe2656b43b44aa2cdc3/) Amazon · US, MA, North Reading [Design jobs](/functions/design/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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