[Skip to main content](#main-content) [ OpenNash ](https://opennash.com/) / [Jobs](https://jobs.opennash.com/) [ 01 Search jobs](https://jobs.opennash.com/search/)[ 02 Companies](https://jobs.opennash.com/explore/)[ 03 Hiring report](https://jobs.opennash.com/reports/hiring/)[ 04 AI assistants](https://jobs.opennash.com/connect/)[ 05 How it works](https://jobs.opennash.com/methodology/) Broadcom · Fort Collins, Colorado, USA # ASIC Design - Floorplan Engineer Fort Collins, Colorado, USA Full-time Design Listed on Broadcom’s official careers site. Posted October 30, 2026. Check that it is still open and apply there. [Apply on Broadcom’s careers site →](https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-Colorado-Fort-Collins-4380-Ziegler-Road/ASIC-Design---Floorplan-Engineer_R027510-3) [OpenNash Jobs](https://jobs.opennash.com/) / [Broadcom](https://jobs.opennash.com/companies/broadcom/) / ASIC Design - Floorplan Engineer ## Job description ### Please Note 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. ### Job Description Be part of the Custom Silicon Design Team within Broadcom’s ASIC Products Division in beautiful Fort Collins, Colorado. Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular, Networking, Computing, and Storage products. This Floorplan Engineer role focuses on chip-level physical architecture and integration for advanced ASICs operating at speeds exceeding 1 GHz, from concept through production. The position provides hands-on experience with the latest 3 nm and smaller process nodes, defining and optimizing the overall die layout, including partitioning, hierarchy, and placement of major functional blocks, memories, and I/O structures for AI, computing, and networking SoCs. ### Key Responsibilities Define and optimize top-level floorplan architecture, including die size estimation, hierarchy definition, and partitioning. Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization. Collaborate closely with RTL, timing, and packaging teams to balance performance, power, and area (PPA) targets. Lead top-level timing closure, congestion analysis, and ECO implementation to ensure clean tapeout readiness. Coordinate with block owners and integration teams for smooth block-level to top-level convergence. Support cross-functional design integration, providing guidance and technical support to internal and external partners. Apply a deep understanding of block PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results. Contribute to design flow automation and methodology development for advanced process technologies. Technical Skills / Background Strong foundation in VLSI design principles and ASIC physical design fundamentals. In-depth experience with floorplanning, die partitioning, and hierarchical design. Working knowledge of PLLs, clock networks, power delivery, and timing-critical structures. Proven ability to drive PPA optimization through innovative layout and planning strategies. Coding & Tool Proficiency Strong experience with TCL scripting and Linux environments is required. Proficiency in Python, Perl, or Ruby is preferred. Experience with Cadence or equivalent physical design tools is highly desirable. Collaboration and Leadership Excellent communication, organizational, and problem-solving skills. Ability to work effectively with customers and cross-functional teams across global sites and time zones. Skilled at organizing and presenting large data sets, managing multiple priorities efficiently. Exercises independent judgment and strong engineering insight in defining methods, techniques, and evaluation criteria. Provides technical leadership, mentors others, and leads execution of new initiatives. ### Education and Experience BS in Electrical or Computer Engineering with 12+ years of relevant experience, or MS in Electrical or Computer Engineering with 10+ years of relevant experience. Compensation and Benefits The annual base salary range for this position is USD To USD As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements. ### Broadcom offers a competitive and comprehensive benefits package Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence. ## At a glance - Posted by the employer: Oct 30, 2026 - First seen by OpenNash: Nov 1, 2026 - Last checked: Nov 1, 2026 - Listed for: 2 days - Location: Fort Collins, Colorado, USA - Employment type: Full-time[Apply on Broadcom’s careers site →](https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-Colorado-Fort-Collins-4380-Ziegler-Road/ASIC-Design---Floorplan-Engineer_R027510-3) ## Hiring at Broadcom - Open jobs: 372 - New in the last 7 days: After two weekly collections - Tracked since: Jul 10, 2026 [All Broadcom jobs](https://jobs.opennash.com/companies/broadcom/) · [Weekly hiring report](/reports/hiring/) ## More jobs at Broadcom ### [ASIC Design Automation Engineer](https://jobs.opennash.com/companies/broadcom/jobs/d9b07fa434b98cde31bd/) Fort Collins, Colorado, USA ### [ASIC Design Engineer](https://jobs.opennash.com/companies/broadcom/jobs/21818554d457b8525d87/) Fort Collins, Colorado, USA ### [ASIC Package Design Project Manager](https://jobs.opennash.com/companies/broadcom/jobs/49f63f72d5185439e215/) Fort Collins, Colorado, USA ### [Design Engineer](https://jobs.opennash.com/companies/broadcom/jobs/afcc507d8dbb636e8272/) Fort Collins, Colorado, USA ## Similar jobs at other companies ### [ASIC Floorplan Design Engineer - New College Grad 2026](https://jobs.opennash.com/companies/nvidia/jobs/8e358841c56200d722b1/) NVIDIA · US, CA, Santa Clara ### [ASIC & FPGA Design Engineer](https://jobs.opennash.com/companies/lockheed-martin/jobs/e94b640c48ecc099615e/) Lockheed Martin · Liverpool, NY ### [ASIC & FPGA Design Engineer - E2](https://jobs.opennash.com/companies/lockheed-martin/jobs/4510ab87f7a931bd10e6/) Lockheed Martin · Liverpool, NY ### [Principal ASIC Design Engineer](https://jobs.opennash.com/companies/fortinet/jobs/9286f067ac1219e2ec7e/) Fortinet · Sunnyvale, CA, United States ### [Digital ASIC Design Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/208c975103db0801757a/) Qualcomm · San Diego, California, United States of America OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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