[Skip to main content](#main-content) [OpenNash Jobs](https://jobs.opennash.com/) [Hiring report](/reports/hiring/) · [All Broadcom jobs](https://jobs.opennash.com/companies/broadcom/) · [Search jobs](/search/) Broadcom · Singapore-Yishun # Senior DFT engineer Singapore-Yishun Full-time Senior individual contributor Operations Listed on Broadcom’s official careers site. Posted October 9, 2026. Check that it is still open and apply there. [Apply on Broadcom’s careers site →](https://broadcom.wd1.myworkdayjobs.com/External_Career/job/Singapore-Yishun/Senior-DFT-engineer_R027389) [OpenNash Jobs](https://jobs.opennash.com/) / [Broadcom](https://jobs.opennash.com/companies/broadcom/) / Senior DFT engineer ## Job description ### Please Note 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. ### Job Description We are seeking a highly motivated Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development team. The successful candidate will be responsible for implementing and verifying DFT solutions across complex hierarchical designs. This position involves hands-on work in DFT insertion, and comprehensive DFT verification to ensure first-pass silicon success. You will collaborate closely with Physical design team, ATE test teams to develop efficient, high-quality test strategies aligned with industry standards. Key Responsibilities a) - Develop and implement DFT architectures for hierarchical SoC and ASIC designs, including both block-level and top-level DFT integration. b) - Perform scan insertion, test point insertion, and test compression using SSN or equivalent compression architectures. c) Validate Serial Stream Network (SSN) topology, managing scan chain balancing, clock domain crossings. d) Integrate Boundary scan (IEEE 1149.x) and other test access mechanisms for chip-level testability. e) - Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to ensure optimal test coverage. f) Perform DFT verification, including verilog / gate level simulation g) - Work closely with cross-functional teams to resolve DFT/testing timing challenges. i) - Collaborate with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility and production readiness. j) - Support silicon bring-up, production test debugging through Diagnostics and failure analysis. ### Qualifications Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field. Minimum 3 years of experience in DFT design and verification (5+ years preferred for senior roles). Strong understanding of scan-based test architectures, test compression, and hierarchical DFT implementation. Hands-on experience with DFT tools such as Siemens Tessent. Proficiency in ATPG generation, fault coverage analysis, and gate-level DFT verification. Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne. Strong scripting skills in TCL, Perl, or Python for DFT automation. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence. ## At a glance - Posted by the employer: Oct 9, 2026 - First seen by OpenNash: Oct 11, 2026 - Last checked: Oct 18, 2026 - Listed for: 9 days - Location: Singapore-Yishun - Employment type: Full-time[Apply on Broadcom’s careers site →](https://broadcom.wd1.myworkdayjobs.com/External_Career/job/Singapore-Yishun/Senior-DFT-engineer_R027389) ## More jobs at Broadcom ### [CAD Engineer](https://jobs.opennash.com/companies/broadcom/jobs/3b2bab1e4acefadd4a30/) Singapore-Yishun ### [Foundation IP Memory Verification Engineer](https://jobs.opennash.com/companies/broadcom/jobs/2dc8f9d1ddb27b3fa756/) Singapore-Yishun ### [IC Layout Engineer](https://jobs.opennash.com/companies/broadcom/jobs/1d0e43578a866dcbef3c/) Singapore-Yishun ### [Staff Layout Engineer](https://jobs.opennash.com/companies/broadcom/jobs/54ab6a5be3a6a1692210/) Singapore-Yishun ## Similar jobs at other companies ### [DFT Engineer](https://jobs.opennash.com/companies/qualcomm/jobs/476a0f5dc693fa809de3/) Qualcomm · Bangalore, India ### [Senior Engineer - DFT](https://jobs.opennash.com/companies/qualcomm/jobs/603449b2baa287286843/) Qualcomm · Bangalore, India ### [Senior Staff Engineer - DFT](https://jobs.opennash.com/companies/infineon-technologies/jobs/5702acfeb94ca275a2dc/) Infineon Technologies · Bangalore ### [Staff Engineer DFT](https://jobs.opennash.com/companies/infineon-technologies/jobs/899d0b5e78dad03ff830/) Infineon Technologies · Ho Chi Minh City ### [DFT Engineer- eInfochips](https://jobs.opennash.com/companies/arrow-electronics/jobs/061cc6762fc7958559ad/) Arrow Electronics · Garden, Bangalore-, Karnātaka, India [Operations jobs](/functions/operations/) OpenNash lists jobs from employers’ own careers sites and does not handle applications. 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